Design Project

Bharath Kumar R

+919*********, 080******** ***************@*****.***

Career Objective

Post-Graduate in VLSI and Embedded System Domain looking for Job and explore opportunities in a Semiconductor industry.

Training in VLSI Design

Undergone training on CMOS circuit Design & Layout Design organized by Mission VTU 10k Empowerment VLSI Design program for a period of 2 months in M S Training & Research Activity Center

Tools used are Cadence Virtuoso v6 and Electric for CMOS circuit design & Layout design, HSPICE tool.

Project on 32-bit SRAM design & decoder and aware about DRC rules & Layout rules. Technical Skills

Design Tools: Xilinx Project Navigator Design suite, Cadence Virtuoso v6.0 tool

(Schematic & Layout Design), HSPICE tool, Electric tool, Mentor Graphics (Schematic & Layout) tool.

Programming language: VHDL & Verilog Programming, System Verilog-Basic, SPICE, Assembly language, C and MATLAB Programming.

Hardware Platforms: Spartan 2 & 3, Virtex 2 pro & 5. Academic Credentials

M.Tech in VLSI Design and Embedded system, College - RNS Institute of Technology - Bangalore, University - VTU, Percentage – 81.37%, Year - 2014

Bachelor of Engineering in Electronics and Communication, College - City Engineering College - Bangalore, University - VTU, Percentage - 65.65%, Year – 2011

Diploma in Electronics and Communication, College - Raman Polytechnic - Bangalore, University - DTE, Percentage - 62.89, Year - 2008

SSLC, School - Gnana Bhodini High School, Percentage - 62.08%, Year – 2005 Projects Details

M.Tech Academic Project on “Design and Implementation of Multiprocessor System on Chip, Interconnected via Bus Architecture” using VHDL. Here in this project different processors architecture is implemented and then they are combined to form MPSoC along with external memory & Arbiter. Architecture implemented is MIPS (Multi-cycle & Single-cycle) & Pipeline Architecture. Duration : 6 months

Tool used : Xilinx Design Suite 10.1v (Project Navigator) Simulation : Modelsim v6.4 & Chip-scope analyzer

Hardware : Virtex 5 FPGA

Miniproject on “Design and implementation of 32-bit RISC Processor” using VHDL. Processor Implemented is MIPS Multi-cycle which is of 32-bit. Along with this different architecture of multiplier, adder & sub-tractor are designed for ALU unit in processor. Duration : 3 months

Tools used : Xilinx Design Suite 10.1v (Project Navigator) Simulation : Modelsim v6.4

Miniproject on “Design and Implementation of 32-Bit Arithmetic and Logical Unit

(ALU)” using VHDL.

ALU unit is designed by combining a brawn multiplier architecture, adder/sub-tractor architecture, Barrel shifter & logical unit. Each architecture designed is of 32-bit. Duration : 3 months

Tools used : Xilinx Design suite 10.1v (Project Navigator) Simulation : Modelsim v6.4

Project on “32-bit SRAM design & decoder design” in 180nm technology. Duration : 2 months

Tool used : Cadence Virtuoso v6

Academic Project on “Intelligent power saver“

It’s purely an Embedded Project with three sensors playing a role to reduce power consumed by components.

Academic Project on “Missile tracking system”

It’s an embedded project using 89c51 Microcontroller here basically we are tracking the infrared signal coming from the missile.

Area of Specialization

CMOS VLSI design Techniques

Digital Layout design

Analog & Mixed signal system

SoC design

Achievements

Got highest marks in 1st and 2nd year of M.Tech & cash prize for the same.

Best paper Award 2nd place in National Conference organized by RNSIT, Bangalore for M.Tech Academic Project

Got 2nd place for Best Project on “INTELLIGENT POWER SAVER” system. Paper submission

Paper Title : “Design and Implementation of MPSoC, Interconnected via Bus Architecture” using VHDL.

In National Conference on Recent Advances in Communication Networks – NCRACN’14 organized by Department of Electronics and Communication Engineering RNS Institute of Technology Bangalore on March 21-22, 2014.

Paper Title : “Design and Implementation of 32-bit ALU unit” using VHDL. In National Conference on Recent Advances in Electronics and Communication Engineering – NCRAECE’13 organized by Department of Electronics and Communication Engineering RNS Institute of Technology Bangalore on May 2013 issue page no 89. Personal Details

Name : Bharath Kumar .R

Date of Birth : 13 August 1989

Permanent Address : #17th, 7th Cross, Ullal Main road, Gnanajoythinagar Bangalore-56 Languages Known : English, Hindi and Kannada

Nationality : Indian

Declaration

I hereby declare that above mentioned information furnished is true to the best of my knowledge

Place : Bangalore Bharath kumar. R

Date :

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