Verilog, System verilog, UVM

Gajanan T. Borkar

Max PG Near Relience mart Email: ****************@*****.***

Arekare Gate, BG Road -Bangalore

Karnataka -560076 Mobile: +919*********

Career Objective

To work in VLSI Domain where performance is rewarded with new responsibilities with knowledgeable environment and to grow along with the organization as a core member of the same.

Synopsis

A Trained Candidate with B.E Degree in Electronics Engineering from Nagpur University, Nagpur. Posses’ Knowledge VLSI Designing & Verification, PCB Designing.

Summary of Qualifications

Good understanding of the ASIC design flow

Experience in writing RTL models in Verilog HDL and

Testbenches in SystemVerilog and UVM

Experience in using industry standard EDA tools for the front-end design and verification

VLSI Domain Skills

HDLs : Verilog

EDA Tool : Questasim and ISE

Knowledge : RTL Coding, FSM based design, Simulation,

Professional Qualification

Maven Silicon Certified Advanced VLSI Design and Verification course

From Maven Silicon VLSI Designing and Training center, Bangalore

Bachelor of Engineering - Wainganga College of Engineering Nagpur, University of Nagpur, Maharastra, India Discipline : Electronics Engineering Percentage : 66.47% ( First Class) (Year : Aug 2010 - July 2014)

HSC : (Maharastra State Board, Year-2010, 65.68% First Class )

SSC : (Maharastra State Board, Year-2007, 62.62% First Class )

Work Experience

Currently working in Maven Silicon as a Project Intern from Jan 2015.

EXTRA CURRICULAR ACTIVITIES

Won 1st prize in Circuit cirque a National Level Bread Board Competition organized by College .

Certificate of Robotics workshop(IIT Mumbai).

Certificate of 8051 & Embedded System workshop(IIT Delhi).

Worked as a Coordinator in National Level event organized by College.

VLSI Projects

AHB-APB Bridge – RTL design and Verification

HDL : Verilog

EDA Tools : Questasim and ISE

Duration : 1.5 Month

Responsibilities:

Architected the design

Implemented the RTL using Verilog HDL independently

Architected the class based verification environment using UVM

Generated functional Coverage for the RTL Verification

Working on AXI -4 Verification (VIP)

EDA Tools : Questasim

Responsibilities:

Architected the class based verification environment using UVM

Building a verification IP.

Will Generate functional Coverage for the RTL Verification

UART - IP Core Verification

HDL : Verilog

EDA Tools : Questasim and ISE

Duration : 1 Month

Responsibilities:

Architected the class based verification environment using UVM

Verified the RTL Module using UVM

Generated functional Coverage for the RTL Verification

Synthesized the design

SPI -Core Verification

HDL : Verilog

EDA Tools : Questasim and ISE

Duration : 1 Month

Responsibilities:

Architected the class based verification environment using UVM

Verified the RTL Module using UVM

Generated functional Coverage for the RTL Verification

Synthesized the design

Dual Port RAM - Verification

HDL : System Verilog EDATools : Questasim and ISE

Duration : 15 Days

Responsibilities:

Implemented dual port Ram using verilog HDL independently

Architected the class based verification environment using System Verilog

Verified the RTL Module using System Verilog

Generated functional Coverage for the RTL Verification

Router 1x3 – RTL design and Verification

HDL : Verilog

EDA Tools : Questasim and ISE

Duration : 20 Days

Description : The router accepts data packets on a single 8-bit port called data and routes the packets to one of the three output channels, channel0, channel1 and channel2.

Responsibilities:

Architected the design

Implemented the RTL using Verilog HDL

Architected the class based verification environment using UVM

Verified the RTL Module using UVM

Generated functional Coverage for the RTL verification

Synthesized the design

References

On Request Gajanan T. Borkar

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