Hardware Engineer, System Software Engineer, Computer Engineering, C++

Nilufar Ferdous

*** **** ******* ****, ***# ***, San Jose, CA 95134

Tel: 210-***-****

Email: *******.*******@*****.***

Objective I am actively seeking a fulltime/part-time position in semi-conductor industry where I can share my skills in research and development.

Summary Strong background in Computer Architecture including Multicore Memory Sub- System, Workload Characterization and Processor/CPU Performance Analysis.

In-depth knowledge in various Cache-Coherence Protocols, Prefetching Techniques and Super-Scalar Processor Design.

Strong background in enhancing GEMS, MARSS simulator, C/C++, SLICC Programming Language, Generic and STL Programming.

Highly organized and self-motivated; quick-learner; skilled communicator; able to maintain cultural sensitivity; innovative and capable of thinking critically. Education University of Texas at San Antonio

Masters in Computer Engineering 2012-2014

Thesis: Improving Chip Multiprocessor Performance by Exploiting Dynamic and Speculative Updates.

Professional and

Research Experience

Performance Architecture Intern, Samsung Austin Research and Development Center (SARC)

Austin, Texas 2014-2015

Awards in Samsung Research

● Award of Excellence in Performance Architecture Internship Project Accomplishments

● Fingerprinting Traces Using Non-Micro Architectural Components

I designed and developed a Register Traffic Characterization Engine called RTE by utilizing several advanced libraries of C++ including Boost, Regex, etc. RTE is capable to extract various information including Register Dependency Distance, Register Reuse Degree, etc. from the fingerprint of traces. I performed various types of unit testing and debugging in RTE with a large variety of benchmarks as Hadoop, SPEC, etc.

I also developed a Pattern Recognition Engine to recognize and parse the ARMv8 instructions based on the mnemonics available in ARMv8 instruction set.

● Clustering and Classification of Traces

Worked on clustering the traces using JMP pro software using

Principal Component Analysis

Linear Discriminate Analysis

K-Mean Clustering

● Familiarization with in-house Simulators and Tools

Exploited two Samsung in-house simulators to collect fingerprints of traces and IPC of different benchmarks respectively. Research Assistant, Department of Electrical and Computer Engineering, University of Texas at San Antonio

San Antonio, Texas 2012-2014

Publications

● Nilufar Ferdous, Byeong Kil Lee and Eugene John, “Performance Enhancement in Shared-Memory Multiprocessors using Dynamically Classified Sharing Information” In IEEE IPCCC 2014.

● Nilufar Ferdous, Byeong Kil Lee and Eugene John. “Exploiting Reuse- Frequency with Selective and Dynamic Updates in an Enhanced Directory Based Coherence Protocol”, In PDPTA 2014.

● Nilufar Ferdous, Byeong Kil Lee, Eugene John “An Adaptive Cache Coherence Protocol exploiting Last Write Update Policy in a CMP” (Completed).

● Nilufar Ferdous, Byeong Kil Lee, Eugene John “A Prediction Based Cache Coherence Protocol Exploiting Reading-Threshold in a CMP” (Completed). Project Accomplished

● Performance Evaluation of Non Uniform Cache Architecture (NUCA) in Chip Multi-Processor (64 core) using GEMS, GARNET and SIMICS simulators. Parsec Benchmark was used for the performance evaluation.

● Analysis of GSHARE and YAGS Branch Predictor in a Chip Multiprocessor exploiting MOESI Cache Coherence Protocol (16 core). The project was done using OPAL, GEMS, RUBY, GARNET and SIMICS.

● Design, implementation and synthesis of a 64-bit pipelined architecture to support a subset of MIPS ISA using Xilinx, Verilog and Credence Encounter.

● Performance analysis of SPEC-2000 using Simple Scalar.

● Performance Evaluation of various prefetchers including SANDBOX PREFETCHER using MARSS simulator.

● Design and Synthesis of a 64-bit RISC Stored-Program Machine using Xilinx and Verilog.

● Online Chatting Messenger (Java).

Awards

● ECE FELLOWSHIP, UTSA Collage of Engineering, Jan 2012- Dec 2013.

● VALERO COMPETITIVE RESEARCH SCHOLARS, UTSA Collage of Eng., Jan 2012- Dec 2013.

Skills ● Simulators: GEMS, MARSS, GARNET, RUBY, OPAL, SIMICS, SIMPLESCALAR

● Languages: Assembly, C, C++, SLICC, Java, Python, Bash

● Tool: Cadence design tools, Credence Encounter, STF_tools(Samsung In-house ), JMP, Xilinx ISE, ModelSim

● Operating System: Windows, Linux

References 1. Dr. Byeong Kil Lee, Vice President, Samsung Research, Korea, ********@*****.***.

2. Rodney Schmidt, Principal Engineer, Samsung Austin Research and Development, *.*******@*******.***.

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