Engineer Engineering
Resume:
ELAMARAN A
**, **** ******, ********, ********-**8181, Tamilnadu, India.
Mob: +91-850*******, e-mail: acr6sg@r.postjobfree.com OBJECTIVE
Looking for a responsible position in an organization where I can serve with my vast knowledge and technical expertise as a design Engineer. As an electronics engineer with a view to utilize and enhance my skills towards professional growth EDUCATIONAL QUALIFICATION
2015 MASTER OF ENGINEERING -VLSI DESIGN with 7.08 CGPA (FIRST CLASS) K.S.Rangasamy College of Technology (AUTONOMOUS) Anna University, Chennai. 2013 BACHELOR OF ENGINEERING - ELECTRONICS AND COMMUNICATION ENGG. (ECE) With 7.88 CGPA (FIRST CLASS) King College of Technology, Anna University, Chennai. 2010 DIPLOMA - ELECTRONICS AND COMMUNICATION ENGG. (DECE) with 87.92% (DISTINCTION)
The Salem Co-Operative Sugar Mills Polytechnic College (GOVT AIDED COLLEGE) 2007 HSC with 60.3% (FIRST CLASS)
Government Higher Secondary School, Pothanur.
2005 SSLC with 66.2% (FIRST CLASS)
Government Higher Secondary School, Pothanur.
PROFILE SUMMARY
Hands of Experience of RTL Coding in verilog, simulation, Dynamic timing analysis and formal verification.
Hands of Experience of Gate Level Simulation (GLS) and Synthesis using timing constraints in Design compiler
(Synopsys). Good Understanding of Static Timing Analysis (STA).
Good Knowledge in Floor Plan, Power Plan, RC Extraction and Physical Verification.
Good Knowledge and understanding on Physical Design (RTL to GDS II) and timing constraints.
Knowledge in VLSI design flows, Digital and Analog design methodologies and Standard Cell Libraries.
Good Knowledge to write, simulate verilog code by using VCS (Synopsys), Chip Scope (Xilinx ISE) and Questasim.
Knowledge of ASIC design flows and good knowledge of using commands in LINUX operating systems. COMPUTER PROFICIENCY / TOOLS
LANGUAGES VERILOG, VHDL, C, C++.
OPERATING SYSTEM RHCE (REDHAT LINUX EL6), Windows Family.
TOOLS SYNOPSYS -VCS, DESIGN COMPILER.
CADENCE - VIRTUOSO, ENCOUNTER.
MENTOR GRAPHICS - QUESTASIM, MODELSIM.
XILINX ISE 14.2, Tanner EDA.
CO - CURRICULAR ACTIVITIES
Nature and Title of
the program
attended
Title Name of the Organizer Period
From To
prize
won
INTERNATIONAL
Journal
High Energy Time
Domain Thermal Sensor
for SOC Thermal
Management
International Journal of
Inventions in Computer
Science and Engineering
04-04-15
IEEE International
Conference
High energy time domain
temperature sensor for
On Chip Thermal
Management
Saveetha Engineering College,
Chennai.
A National
Workshop
Analog and Digital IC
design using CADENCE
TOOL
M.Kumarasamy College of
Engineering
SYNOPSYS Course Advanced ASIC Design
using SYNOPSYS EDA
TOOLS
KSRCT VLSI
Design Center
A National Level
Technical
Symposium
Code debugging Tamilnadu College of
Engineering. Coimbatore
11-04-13 First
prize
National Level Paper
Presantation
On chip Temperature
Measurement
Tamilnadu College of
Engineering. Coimbatore
11-04-13 Second
Prize
Course JAVA HCL
Linux(EL6)
Course
RH SA3 REDHAT
System Administration-
III
REDHAT **-**-**-**-**-**
Linux(EL6)
Course
RH SA2 REDHAT
System Administration-
II
REDHAT **-**-**-**-**-**
Linux(EL6)
Course
RH SA1 REDHAT
System Administration-
I
REDHAT **-**-**-**-**-**
ORACLE
Workforce
Development
Program
AWARD OF
ACHIEVEMENT
(Web Component
Development using Java
Technologies)
ORACLE 26-10-12
Workshop Embedded system ARROW Creative Academy 26-07-12 Project Expo Mobile phone charger
using without current
King College of Technology 08-03-12
Workshop Managerial workshop for
personal and personnel
AIM Institute 09-12-09
AREA OF INTEREST
Digital VLSI Design
ASIC Design and Verification
Physical Design
Analog physical Design
PG PROJECT: HIGH ENERGY TIME DOMAIN THERMAL SENSOR FOR SOC THERMAL MANAGEMENT DESCRIPTION
The temperature variations significantly affect the performance and reliability of highly integrated chips. The calibrated digital thermal sensor is used for on chip temperature sensing applications. In this project is proposed for on- chip thermal management. The proposed design uses to perform self-calibration, and thus effects of process variation can be removed.Synthesized report of area, timing and power report is carried out from SYNOPSYS DESIGN COMPILER (90 nm TECHNOLOGY).
EXTRA-CURRICULAR ACTIVITIES
Student member of IEEE
Essay writing in social awareness
Got 35.534 marks in TANCET
Head of my Diploma Project
PERSONAL STRENGTHS
Willingness to learn new technology and can adopt a new environment and culture
Punctual, easily adaptable
Strong Leadership and motivational skills
Hard Work and patience
PERSONAL DETAILS
FATHER'S NAME : Anbumani S
D.O.B : 13/05/1990
MARITAL STATUS : Single
LANGUAGES : English(R W S), Tamil(R W S),
HOBBIES : Pencil Sketching, Playing cricket
DECLARATION
I hereby declare that all the above given details are true with the best of my knowledge. Date : 21/ 10/ 2015
Place : Namakkal (ELAMARAN A)
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