ASIC Design and Verification Trainee

Curriculum Vitae

Pravin Shivshankar Shete Email: acr6m3@r.postjobfree.com

M.Tech (VLSI Design) Mobile: +91-758*******, 805*******

Career Objective:

To become a successful professional in the field Electronics and VLSI Design, work in a creative and challenging environment where I can use the best of my knowledge in the development of the organization.

Internship Experience:

Aadi Semicon Solutions Pvt. Ltd., Bengaluru.

Intern, November 2014 – April 2015.

Verilog design – SPI, FIFO

SV Environment – SPI, I2C

UVM Environment – I2C, APB

Technical Summary:

HDL : VHDL, Verilog HDL, System Verilog and UVM

Protocols Known : AMBA AXI, AHB, APB, SPI, I2C and Basics of DDR

Software : Questa-sim, Xilinx, Modelsim

Platform : Windows 7, LINUX

Educational Qualification:

Completed M.Tech in Electronics-VLSI Design from College of Engineering, B. V. D. University, Pune with CGPA 9.3 (2012-14).

Completed B.E. in Electronics and Communication from Marathwada Institute of Technology, Dr. B. A. M. University with 64.93% (2007-11).

HSC from Shiv-Chhatrapati College of Science, Aurangabad with 71.83% (2005-07).

SSC from Dnyan Prakash Vidya Mandir, Aurangabad with 74.8% (2004-05).

Project:

M.Tech:

Project Name: Design of AMBA AHB master and arbiter for on-chip bus architecture (Jan - August 2014).

Description: Reconfigurable arbiter that can interface with any common IP core of a system, using specification of AMBA bus protocol. The arbiter plays a very important role to manage the resource sharing on the SOC platform and also, ensures that only one bus master at a time is allowed to initiate data transfers. Master is the one who can initiate the transfer. I have designed these modules using Verilog HDL.

Co-curricular Activities:

Published paper in journal IJAIEM and IJACSSE on AMBA 2.0 AHB.

Presented paper in National conference on AMBA 2.0 AHB, Pune.

Presented paper in National conference on DDR-SDRAM, Pune.

Attended International Conference on Nano-Technology at College of Engineering, B. V. D. University, Pune.

Won first prize in RC car held at Government Engineering College, Aurangabad.

Personal Details:

Name : Pravin Shivshankar Shete.

Date of Birth : 27th June, 1990.

Gender : Male.

Marital Status : Single.

Languages Known : English, Hindi and Marathi.

Nationality : Indian.

Permanent Address : Plot No. C-1/72, Gajanan nagar, Aurangabad - 431005.

Present Address : 683, Cloud-9 PG, 17th Cross road, J P Nagar 6th phase,

Puttenhalli main road, Bengaluru – 560078.

Declaration

I hereby declare that the information furnished above is true to the best of my knowledge.

Date: / /

Place: Bengaluru ( Pravin S. Shete )

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