Project Design Engineer

Profile Information

Name: Rajesh Babu Sanaka Email: acr6av@r.postjobfree.com

Phone: 973-***-**** Address: #1239

32nd G cross

Jayanagar (4th T-block)

Bengaluru

Karnataka-560041

Career Objective

Looking for an opportunity to work as a physical design engineer in dynamic work environment.

Core Competancy

Good knowledge of network analysis.

Good knowledge about ASIC design flow.

Good knowledge on NETLIST to GDSII flow.

Good knowledge of digital design.

Good knowledge of static timing analysis concepts. Understand the working of basic CMOS inverter and fabrication process of an IC. Basic knowledge of second order effects of cmos like body effect, channel length modulation. Basic knowledge of power reduction techniques.

Basic Knowledge on antenna violations & cross talk effect. Hands on experience on IC compiler, Primetime .

Education Details

Degree Discipline School/College

Year of

passing

Aggregate

PG

Diploma

Advanced Diploma in ASIC Design RV-VLSI Design Center 2015 - Degree Electrical and Electronics

Sunflower College Of

Engineering&Technology.

2014 66

PUC - Narayana Junior College 2010 81.5

SSLC - Nava Jeevan High School 2008 76.6

Project Details

Project Title Block level physical design of torpido for 180nm. Institute Name RV-VLSI

Project

Description

Torpedo sub block includes 32 macros,43275 standard cells with supply voltage 1.8v, working operating frequency of 400MHZ, it has total 5 clocks (3 propagated and 2 generated),5 metal layers used, FAB:jazz semiconductor,180nm technology node used.

Tools Used ICC,Prime Time from synopsys, Calibre from Mentor Graphics. Challenges

1.Placement of macros with congestion free floor plan. 2.Deciding number of power straps to get IR drop (VDD+VSS) less than 5% of 1.8v. 3.Analyzing timing reports.

Project Title Analyzing different timing reports with OCV. Institute Name RV-VLSI design center.

Project

Description

1.Generation and analysis of timing reports for different designs in various scenarios with MCMM. 2.Analysis of CRPR and effect of uncertainty. 3.Understanding the effect of clock skew on timing. 4.understanding various techniques to fix violations.

Tools Used Prime time from Synopsys.

Challenges

1. Dealing with false path and multi-cycle paths. 2. Analysis of latch based designs. 3. Analysis of Signal Integrity/cross-talk. Project Name

Performance of Voltage and Frequency Controller in Isolated Wind Power Generation For a Three-Phase Four-Wire System.

Institute Name Sunflower College Of Engineering&Technology. Project

Description

It deals with a new control algorithm for a voltage and and frequency controller

(VFC) of an isolated wind energy conversion system (IWECS). Challenges Understanding the performance of wind power generation system. Tools MATLAB.

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