ACHUTHAN KN
Mobile No: +91-994*******
acr57k@r.postjobfree.com
Objective
Obtain the position of project management with excellent leadership qualities, which includes organizing, problem solving, managing budgets and planning skills.
Skills
VLSI
Domain
ASIC / FPGA front-end Design and Verification
Technical knowledge
RTL coding, Synthesis, FSM designs, Code Coverage, Functional coverage, CMOS, STA.
HDL
Verilog
HVL
System Verilog
TB Methodology
OVM (Open Verification Methodology),
UVM (Universal Verification Methodology).
Verification Methodology
Coverage Driven Verification,
Assertion Based verification – SVA
EDA Tools
Xilinx - ISE, Questasim, Rivera PRO, Modelsim, T-spice.
Embedded System
Language
Embedded C
Controller family
8051, PIC16FXX, MSP430, AVR, Aurdino.
Tools
Keil µ vision, Proteus VSM, AVR studio, Dolphin View, MATLAB, ARES, ENERGIA for MSP430
Operating System
Windows, Linux.
Software Skills
Flash, Dreamweaver, Corel Draw, Adobe Photoshop, MS office.
Computer Languages
C, C++, HTML, Perl.
Academic Credentials
Degree
Year
School/College
Board / Univ
Percentage
B.E. - Electrical and Electronics Engineering
2014
Angel College of Engineering and Technology, Tirupur
Anna University
73.3 %
HSC
2010
Velammal Matric Hr. Sec. School, Madurai
State Board
82%
S.S.L.C
2008
KendriyaVidyalaya, Madurai
CBSE
68%
Work Experience
Company
Indowind Energy Ltd, Chennai
Experience
May 2014 – June 2015
Role
Maintenance Engineer
Responsibilities
Have to rectify the faults in the wind mill and also have to develop embedded based projects.
Company
Maven Silicon, Bangalore
Internship
July 2015 – January 2016
Role
ASIC / FPGA Design and Verification trainee
Responsibilities
Have to learn and implement the concepts of synthesizable rtl design and also involve in projects on various methods of verification.
Certification
VLSI – RN
Have done a 6 months full time course on VLSI rtl to netlist at Maven Silicon, Bangalore.
Business English Certification
Have certified from UNIVERSITY OF CAMBRIDGE for Business English Certification at Vantage level.
Handled Projects
Router 1 X 3 Design and Verification
Tool
Xilinx, Questasim
Language / Methodology
Verilog, Universal Verification Methodology
Role
Team Leader
Responsibilities
Involved in creating logics to achieve the specified protocol and also constructed reusable test bench verification structure.
Description: It drives an incoming packet to an output channel based on the address field contained in the packet header. The verification methodology which constructed can be reused by altering its configuration at top level.
Dual Port RAM Verification Using System Verilog
Tool
Questasim
Language
System Verilog
Verification Methodology
Assertion based verification - SVA
Role
Team Leader
Responsibilities
Involved in writing up the System Verilog program based on the hierarchical order of classes.
Description: It is a test bench for verifying the rtl code of dual port ram which was written in verilog HDL.
RAM SOC Verification Using Universal Verification Methodology
Tool
Rivera Pro
Methodology
Universal Verification Methodology
Role
Key player
Responsibilities
Involved in constructing the reusable verification methodology.
Description: It is a verification methodology which can be reused by configuring from the top module. The code was written to verifying the rtl code of ram soc which consists of four 4094 x 64 rams.
Embedded based Generator Protection System
Controller
AT89S52
Role
Key player
Responsibilities
Created the design, wrote the embedded program.
Credits
Under testing for implementing in all NEPC type windmill systems.
Description: It considers rpm as a factor during the change of mode fro m G1 mode (600A) to G2 mode (100A) rather than keeping time (current method) as a factor.
Personal Information:
Name
Kochi Nattesan Achuthan
Date Of Birth
28/09/1992
Languages Known
English, Tamil, Hindi, Sourastra
Marital Status
Single
Hobbies
Working in computer and exploring electrical circuits.
Permanent Address
8-A, Komatha west cross st, Karpaga Nagar,Villapuram, Madurai-625 012
Declaration
I hereby affirm that the above information given by me is true to the best of my knowledge and belief. I will solely be responsible for any discrepancy found in them.
(ACHUTHAN K.N)