VLSI Engineer

M. Prashanthi E-Mail: acr3ed@r.postjobfree.com

Design and Verification Engineer Contact: +91-961*******

Professional Summary

•1.8 years of experience as Design and verification engineer in ASIC and FPGA.

•Hands on experience in VLSI design and verification Tools QUARTUSII, MODELSIM.

•Good working knowledge on FPGA Board testing also.

•Extensive work experience on Developing a Product.

•Thorough knowledge on VLSI, and DEGITAL.

•Strong commitment, dedication and efficient in problem solving, truly a team player with excellent technical and communicational skills.

•Enthusiastic about learning new concepts in emerging technologies and domains.

Professional Experience

•8 months Experience as a Design and Testing Engineer (Internship) in Cerium Systems Pvt. Ltd. from Jul’14 – Feb’15.

•1year Experience as a Design and Verification Engineer in NVLogic Technologies Pvt. Ltd. from Feb’11 – Mar’12.

Educational Qualification

•B. Tech from Raja Mahendra College of Engineering with 72.78% in 2010.

•Intermediate from Sri Triveni junior College for Girls with 85.50% in 2006.

•SSC from Sri Saraswathi Shishu Mandir with 84.16% in 2004.

Technical Expertise

•Languages/Applications - Verilog, VHDL, C,C++.

•Operating Systems - Linux, Windows from 2000.

•Software - Xilinx, ModelSim, QuartusII.

Projects

•Voice Interface Unit

Client: Bharat Electronics Limited (BEL).

Domain: Verification Process.

Tools Worked: ModelSim Software, Verilog HDL.

Description: The Portable audio recorder shall be capable of recording two Mono audio inputs for 2 hours of duration on a removable solid state non-volatile memory. The unit shall be capable of dual playback (live/recorded) of any channel. This unit is to be designed and developed for industrial usage.

Responsabilités:

•Developing a Verification Environment.

•Verifying Hardware Design with Test Bench Module.

•Verifying Record and Play of the design module.

•Preparation of Weekly status reports and status calls with clients.

•Exciter Simulator

Client: Bharat Electronics Limited (BEL).

Domain: Hardware Design and FPGA Board testing.

Tools Worked: ModelSim Software, Verilog HDL, QuartusII.

Description: The Exciter Simulator Unit can be accessed by the user through the GUI provided. The unit is connected to the PC through a USB interface of the unit and RS 232 interface of the PC. The Test Pattern generator/analysis logic is implemented using Micro controller and FPGA.

Responsabilités:

•Developing Hardware Modules.

•Testing FPGA and Driver Board by using QuartusII Software and through JTAG.

•Verifying simulator using GUI.

•Preparation of Weekly status reports and status calls with clients.

•Test Simulator for ECM Processor

Client: Bharat Electronics Limited (BEL).

Domain: Hardware Design Development and FPGA Testing.

Tools Worked: QuatusII Software, Verilog HDL.

Description: It is a Test Jig for ECM Processor, up to component level, in order to verify the functionality and enable manufacturing PCB required. The Test Simulator is to be designed to test the ECM Processor in standalone. ECM Processor is connected to the ECM Test jig through a connector. Hardware module will provide DATA, ADDR and Control signals for testing and it will display the DATA, ADDR word send to jig on the LCD display.

Responsabilités:

•Developing Hardware modules.

•Developing TOUCH modules for 4 inches TFT Touch Screen.

•Configuring Test Jig and Testing total Jig with TOUCH Screen.

•Testing FPGA and Driver Board.

Achievements

•Completed VLSI Training Course.

•Utilized modern learning methods such as e-learning and team learning.

• Identified and utilized variety of learning materials, resources and technology methods to support & improve the Product Development environment.

Personal Details

Full Name : M Prashanthi

Gender : Female

Date of Birth : 27th June, 1989

Nationality : Indian

Hobbies : Playing Chess, Listening to Music and Cooking.

Languages Known : English, Telugu and Hindi

Permanent Address : Plot no.37/A, Chaitanya nagar colony, B.N.Reddy nagar,

Pin code 500070.

I hereby declare that the above furnished information is true to the best of my knowledge and I hold the responsibility of its authenticity.

Date: 12-10-2015

Place: Hyderabad M.Prashanthi.

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