Java program database design
Resume:
TAO PU
Dallas, Texas *****
***.**@********.***
OBJECTIVE
An entry-level job to apply knowledge in Java program; database design in July 2015 EDUCATION
University of Texas at Dallas, Richardson, Texas May 2015 Master of Science in Electrical Engineering, Concentrating on Digital Systems, overall GPA: 3.46/4.0
University of Electronic Science and Technology of China, Chengdu, China July 2010 Bachelor of Science in Electrical Engineering, Concentrating on Electrical Automation, GPA: 3.47/4.
SKILLS
SQL; C; JAVA; Python; ASIC; Verilog; Matlab; Spice; Cadence. COURSES TAKEN
Database design; Microprocessor System; Advanced Digital Logic; HDL; Computer Architecture; DSP; VLSI Design; Advanced VLSI; Analog Integrated Circuit Design; INTERNSHIP AND WORK EXPERIENCE
Thyssenkrupp-elevator (China) Co., Ltd, Zhongshan, China Full time as Electrical Engineer at Thyssenkrupp-elevator (China) Co., Ltd. 9/2010-9/2011 ACADEMIC PROJECT
N-body gravity Simulation Design using ARM Cortex M4 (Java; C)
• Employed ARM Cortex-M4 chip to simulate up to 100 body movements. Designed the algorithm of N-body motion based on the universe gravity force and configuration of Interruption, UART, Timers, I/O ports in C. Built GUI on PC in Java to read, write files and communicate with chip and display the N-body motion under universe gravity force.
• Hardware is ARM, software is CCS and Netbeans. Design contains three parts: Embedded system, Serial Port protocol, Java GUI. Use C to implement bouncing ball algorithm and data transmission. Use Java to implement the GUI to visualize performance and Serial Port on PC. Database System Design: Graduate student system Database (Oracle RDBMS)
• Using SQL to design a graduate student system Database.
• Designed EER model, map to relational schema, functional dependency normalization.
• Created queries, trigger and setup views with permission in Oracle Database tools. Performance evaluation of Alpha processor (Python)
• Multi-level Cache for L1 and L2 organizations were designed and simulated with ‘SimpleScalar’. Design Optimized by exhaustive iterations by # of levels, Split/unified configuration, block size, associativity, and replacement policy were analyzed to come up with an optimal cache configuration for Alpha 21264 Processor in terms of Cycles per Instructions (CPI) calculation and Miss rate. Automated process to run simulation for all cache configurations was scripted using Python
Design of low power Programmable Pulse Width Modulator using 0.13µm CMOS technology (ASIC)
• Developed complete Verilog description for the Programmable PWM chip to perform arithmetic and logical operations on a positive clock edge.
• Cell-library characterization done for all gates used (INV, NAND, NOR, XOR, OA221, MUX, ADDER, DFF) in the chip, tested for behavior and timing analysis using HSPICE.
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