NIREESHA RASIRAJU

Sriharipuram (V&P), Vijayapuram(M), Chittoor(D)-517586

E-Mail: acqq11@r.postjobfree.com

Mobile no: +91-879*******

Objective:

To be an efficient VLSI designer in a good organization that will provide a professional and challenging environment to explore and apply my knowledge.

Educational Qualifications:

Education

Institute

Board /University

Year of passing

Percentage

M.Tech

(VLSI Design)

VIT University, Chennai

VIT

2013-Present

8.67

(CGPA)

B.Tech (Electronics and Communications)

K.S.R.M.C.E, Kadapa

SVU

2012

79.7

Intermediate

Sri Chaitanya Junior College, Tirupathi

State Board of Education

2008

96.2

S.S.C

Z.P.P.H School, Sriharipuram

State Board of Education

2006

89.3

Internship:

Intern at INTEL INDIA for a period of 6 months from Jan 2015-June 2015, worked in DFX validation team. In my internship tenure in DFX, I have worked on following toolsets and projects:

Boundary Scan Validation: In GLS, verifying the netlist and ensuring that there should not be any missing devices, open and short circuits, and misaligned devices by testing the IO pads and interconnects between the devices using EXTEST instruction.

Generated Testbench Patterns using Synopsys BSDL compiler to verify the design and verified BSCAN simulations with ZERO delay and SDF’s in all corners using Synopsys VCS. Netlist debugging is done using Synopsys DVE.

In summary, with this BSCAN test validation ensured time to market by reducing the test simulation time and quality of the product.

Technical Skills:

Cadence EDA Tools : NC Sim, RTL Compiler

Technology Library : gpdk180

XILINX

Hardware description language : Verilog

Scripting Language : PERL

Software Language : C

Achievements:

Qualified GATE Exam in 2013 with the score of 455.

Paper “Low Leakage Power Wallace Tree Multiplier design using SVL Circuits” published in International Journal of Advanced Engineering Research (IJAER).

Academic Projects:

1.Performance Analysis of MIMO SFBC OFDM System for AWGN And RAYLEIGH FADING CHANNEL

The main objective of this work is verifying the performance of Orthogonal Division Multiplexed Frequency (OFDM) system by finding the Bit Error Rate (BER) for different values of signal to noise ratio (SNR).

2.Design of Power Efficient Multiplier Using MTCMOS Technique

The main objective of this project is reducing Leakage Power and maintaining the performance as well by using Multi Threshold Complementary Metal Oxide Semiconductor (MTCMOS) technique, in which is we are using two different thresholds on the same design.

3.Low Leakage Power Wallace Tree Multiplier design using SVL Circuits

The main objective of this work is minimization of leakage power, retention of data when the logic circuit is in standby mode using self-controllable Voltage Level (SVL) circuits.

4.ASIC implementation of Wallace Tree Multiplier using Reversible Logic circuits

The main objective of this work is implementing multiplier using reversible logic gates, performing RTL to GDS-II flow and minimizing energy consumption due to loss of information

Personal Details:

Name : R.Nireesha

Father’s name : R.Siva Raju

Date of Birth : 25-06-1991

Nationality : Indian

Language Known : English, Telugu and Tamil

Hobbies : Listening to Music, Playing games

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