Design Engineer
Resume:
Venkatesh. P
Devarapalli(vi),Parchur(md), Email:****************@*****.***
Prakasam(dt),AP. Mobile: +91-740*******
Summary of Qualifications
Good understanding of the ASIC and FPGA design flow
Good knowledge on writing RTL models in Verilog HDL and
Testbenches in SystemVerilog
Very good knowledge in verification methodologies
Experience in using industry standard EDA tools for the front-end design and verification
VLSI Domain Skills
HDLs: Verilog
EDA Tool: Cadance (NCSIM), Questasim and ISE
Domain: ASIC/FPGA Design Flow, Digital Design methodologies
Knowledge: RTL Coding, FSM based design, Simulation,
Code Coverage, Synthesis,
Static Timing Analysis
Programming and Scripting Languages
Programming : C and C++.
Scripting : Perl .
Professional Qualification
Maven Silicon Certified Advanced VLSI Design and Verification course
from Maven Silicon VLSI Design and Training Center, Bangalore
Year: Nov 2014
Master of Science and technology, SOIS College,
Manipal University, Karnataka, India . Discipline: VLSI Designs.
Percentage: 7.12 CGPA.
Year: Dec 2014.
B.Tech -- (JNTU-H, 2012 & 62.45%).
Intermediate – (Board Of Intermediate Education, 2008 & 67.89 % )
SSC -- (Board Of Secondary Education, 2006 & 70%)
Achievements
Won Kabbadi at zonal level competition at Sarada public school.
Organized “Quiz” Competition at Sarada public School
Received the best performer award from Maven Silicon during the VLSI Design course.
Experience
June 2014 – December 2014, Maven Silicon, VLSI Design and Training Center
VLSI Projects
Real Time Clock – RTL design and verification
HDL: Verilog
HVL: SystemVerilog
EDA Tools: Questasim and ISE
Responsibilities:
Implemented the Real Time Clock using Verilog HDL independently
Architected the class based verification environment using SystemVerilog
Verified the RTL model using SystemVerilog.
Generated functional and code coverage for the RTL verification sign-off
Synthesized the design
Router 1x3 – RTL design
HDL: Verilog
EDA Tools: Questasim and ISE
Description: The router accepts data packets on a single 8-bit port called data and routes the packets to one of the three output channels, channel0, channel1 and channel2.
Responsibilities:
Architected the design
Implemented the RTL using Verilog HDL
Verified the RTL using Verilog HDL
Generated code coverage.
Synthesized the desig
Video Graphics Adaptor – RTL Design and Verification
HDL: Verilog EDATools: Questasim and ISE
Responsibilities:
Architected the design
Implemented the RTL using Verilog HDL
Verified the RTL using Verilog HDL
Implemented the design on the Spartan, Xilinx FPGA and verified the design on the board.
Implementation of AMBA-AXI3 protocol
Description:
A project done in Verilog HDL in which AXI protocol has been implemented using MODELSIM tool. AXI is a advance extensible interconnect to which a high performance processor can be connected. This Bus has multiple masters, an arbiter and slaves. Information can be sent either way from Master to Slave and Slave to Master.
References
On Requestssssss
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