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Design Engineering

Location:
Bengaluru, KA, India
Posted:
July 07, 2015

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Resume:

SPANDANA HIREMATH

Phone: +91-814*******

Curriculum Vitae e-mail: acqmgf@r.postjobfree.com

Career Objective:

To work in a healthy, innovative and challenging environment extracting the best out of me, which is conducive to learn and grow at professional as well as personal level thereby directing my future endeavors as an asset to the organization Education

2013-2015 Master of Technology in Digital Electronics, Visveshwaraiah Technological University (VTU) Extension Centre, UTL technologies Ltd, Bangalore. 2009-2013 Bachelor of Engineering in Electrical and Electronics, Navodaya institute of technology Raichur, 69.00%

2007-2009 Pre-University Education, Sharanabasweshwar Residential Composite PU College, Gulbarga, 66.83%

2006-2007 Secondary Education, Sharanabasweshwar Residential Public School, Gulbarga, 84%

Technical Skills:

Programming Languages Visual Basic and Assembly level programming (8085) Operating Systems Windows, Linux- Red Hat

Software 2D Drafting Package: AutoCAD

EDA Tools: Cadence virtuoso, Mentor Graphics Modelsim HDLs: Verilog HDL, VHDL

Application Software: MATLAB, MS Office

Lab Equipment Oscilloscopes, Logic Analyzers and Bus Analyze Academic Projects

2015 M.Tech Thesis:

Designing a High PSRR (Power Supply Rejection Ratio), High Transient response, Efficient and low Area LDO (Low-Voltage Low-Dropout Regulator), for very low voltage applications LDOs have been designed to account for are Soft start, Inrush current limiter and Short Circuit Protection. With Cadence tool in 90nm technology for DDR RAM voltage requirements.

2014 Design and Implementation of on-chip buck-boost converter: Effort to design a fully integrated DC-DC “buck-boost” converter which has a high switching frequency (50MHz) with reduced value of the filter component, integrated dc-dc converters can be used to provide simple, Low-cost solutions for designs when continuous tracking is required.

Tool used: Cadence virtuoso 90nm

2014 DFT Modeling and Test methods for VLSI Systems-Fault modeling the most important topic to understand in testing, this case study gives a good understanding of higher level abstractions

2013 BE Project: Fuzzy Logic Based DC to DC Converter Using Controller It was developed to be used in an automated industries and robotics, continuously monitors parameters (current and voltage) on individual Load and in power management.

Tool used: Microcontroller

Publications:

1. “Design of a fast settling LDO Regulator”, Spandana Hiremath, et. al, selected for participation in “Indian Nanoelectronics User Program” Centre for nanoscience and engineering at Indian Institute of Science, Bangalore, 2015 2. “Design of a Fast Settling Low-Voltage Low-Dropout Regulator”, Spandana Hiremath et. al, ICSET2015, Vellore institute of technology. Achievements and Extra-curricular Activities

“Communication Lead” at IEEE Student Branch UTL Technologies LTD, Bangalore

Runner up at TCS TECH BYTES

Secured first place in Fashion Show (net’s Regal’10)

First place in Variety Entertainment

Personal Details

Date of Birth April 29, 1991

Languages known English, Hindi and Kannada

Hobbies Adventure Sports, Traveling, Social

Service, Reading books, Dancing



Contact this candidate