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Project Training

Location:
New Delhi, DL, India
Posted:
July 07, 2015

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Resume:

CURRICULUM VITAE

KINSHUK CHAUHAN

House no.***,Street no.16,

Rangpuri, Mahipalpur,

New Delhi-110037.

*******.*********@*****.***

Mobile No.: +91-945*******

CAREER OBJECTIVE

Learning the latest in the emerging scenario & applying the best of my knowledge and innovative skills to help with new products and brings more efficiency in an organization.

PROFILE

M.Tech in INFORMATION & COMMUNICATION TECHNOLOGY (specialization -VLSI DESIGN) from GAUTAM BUDDHA UNIVERSITY, GREATER NOIDA (U.P).

B.Tech in ELECTRONICS & INSTRUMENTATION from DEWAN V.S INSTITUTE OF ENGINEERING AND TECHNOLOGY, MEERUT affiliated to Uttar Pradesh Technical University, LUCKNOW (U.P).

EDUCATIONAL AND PROFESSIONAL CERTIFICATION

2015

M.Tech in INFORMATION & COMMUNICATION TECHNOLOGY (Specialization- VLSI DESIGN) from GAUTAM BUDDHA UNIVERSITY Greater Noida.

Score: 8.93 CGPA.

2012

B.Tech in ELECTRONICS AND INSTRUMENTATION from DEWAN V.S INSTITUTE OF ENGINEERING AND TECHNOLOGY, Meerut.

Score: 73.34 %( affiliated to Uttar Pradesh Technical University).

2008

Senior Secondary from BAL VIDYA MANDIR SR.SEC SCHOOL SAMBHAL (U.P) 244302.

Score: 67.60 %( affiliated to C.B.S.E New Delhi).

2006

Secondary from BAL VIDYA MANDIR SR.SEC SCHOOL SAMBHAL (U.P) 244302.

Score: 76.30 %( affiliated to C.B.S.E New Delhi).

CERTIFICATE

6 months basic computer diploma.

4 week basic Verilog training from DKOPS labs pvt ltd Noida.

TECHNICAL & KEY SKILLS

Windows8, windows7, Windows XP.

MS office.

Knowledge of Digital electronics.

Knowledge of Electronics field.

Efficient and Precise Internet Handling.

EDA TOOLS

Xilinx ISE.

Modelsim

Cadence(virtuoso) tool

Multisim

LANGUAGE KNOWN

Verilog

PROJECT & SUMMER TRAINING DETAILS

Organization: Bharat Heavy Electrical Limited (Uttrakhand).

Time period: 4 weeks.

Project work during training: Working with RTD, Thermocouple, Flow Meter, and Sensors.

Major project in B.Tech: Automatic Bottle Filling Station.

M.Tech Mini Project: Field Programmable Gate Array Realization of Microprogrammed Controller based Parallel Digital FIR Filter Architecture.

M.Tech Major Project: SRAM Cell Design for Reducing Leakage in Submicron Technology.

PERSONAL PROFILE

Father name : Chhater Singh Chauhan

Date of Birth : JUNE 18, 1991

Present Address : House no.258, Street no.16, Rangpuri, Mahipalpur,

New Delhi –110037

Marital Status/Sex : Single/Male

Nationality : Indian

Languages Spoken : English, Hindi

DATE:

PLACE:

KINSHUK CHAUHAN



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