Project Engineering

VAISHALY.K

No.* kaveri Nagar,

Thaneer Pandal Road,

Peelamedu

Coimbatore - 641004.

E- Mail :********.***@*****.***

Phone no :+919*********

OBJECTIVE

To work in an environment that utilizes my logical, technical and creative skills for the development of the organization that also enhances my growth in all fields. EDUCATIONAL QUALIFICATION

Course

Institution

Board /

University

Year of

Completion

Marks %

/ CGPA

X

XII

B.E(ECE)

M.E(VLSI Design)

Vivekanandha Vidhya

Bhavan Matriculation Higher

Secondary School,

Tiruchengodu.

Vidhya Vikas Girls Higher

Secondary School,

Tiruchengodu.

Hindusthan College of

Engineering and Technology,

Coimbatore.

PSG College of Technology,

Coimbatore.

Matriculation

State Board

Anna

University

Anna

University

2006

2008

2012

2015(may)

73.26

75.75

8.37

7.05

TOOLS AND LANGUAGE PROFICIENCY:

Languages : Verilog, VHDL,System Verilog,Verilog A, Basics of C++. Scripts : Perl Basics

Packages : Mentor Graphics-Pyxis, Cadence-Virtuoso, SOC Encounter, MATLAB, Xilinx Platforms Used: Windows 8, LINUX

PROJECT WORK UNDERTAKEN:

Project 1: Verification of RAM and Comparators using System Verilog Environment : System verilog

Tool : Mentor graphics-questa sim

OS : Linux

Description : RAM and comparator has been verified using system verilog environment by creating stimulus, interface, scoreboard, monitors, drivers, mailbox . Project 2: Electronic Eye Detector.

Description : Designed hardware for Electronic eye detector which is used for theft control using LDR Project 3: Nobody bias modified SET D-Flip flop for low power VLSI applications. Tool : TANNER EDA

OS : Windows 7

Description : The SET D flip-flop is designed using No Body Bias (NBB) technique with Self Voltage Logic (SVL) and implemented in communication system using 90nm technology Project 4 : Design of Low power Content Addressable Memories (ongoing) Tool : Cadence – Virtuoso, Layout editor

OS : Linux

Description :Content addressable memories has been designed for low power and high performance operation .The proposed design has been used with precomputation technique and showed comparatively better performance than conventional CAM NOR type design using 180nm technology .

TRAINING DETAILS:

Name of the Industry

Duration Areas of Exposure

Mikrosen Control Devices,

Coimbatore

31.05.2010-10.06.2010

Sensors for Industrial

Automation

PSG College of Technology,

Coimbatore

2 days Digital design using Verilog

ELECTIVES :

Hardware-software co-design

Computer aided design

Computer architecture

CO- CURRICULAR ACTIVITIES:

Participated in National Level Technical Symposium and Project fair at CONFIANZA’12 Conducted at Hindusthan College of Engineering and Technology, Coimbatore.

Participated in One day Workshop on “Introduction to Labview for Engineers”, jointly organized by Department of ECE and Innovative Invaders Technologies, held at Karpagam college of engineering, Coimbatore.

Participated in National level workshop on “Image processing” jointly organized by department of ECE and IETE Students forum, held at Hindusthan College of Engineering and Technology, Coimbatore.

Presented a paper entitled “Dynamic Voltage and Frequency Scaling For-Demand Performance and Availability of Biomedical Embedded Systems” in the state level students technical symposium held at Sri Eshwar college of engineering EXTRA CURRICULAR ACTIVITIES:

Event Coordinator of VDAT 2014, International Symposium organized by Department of Electronics & Communication Engineering, PSG College of Technology.

Member of IETE (2010 - 2012).

PERSONAL INFORMATION

Father’s name : P. Krishnamoorthy

Mother’s name : A. Narmadha

Date of birth : 21st March 1991

Nationality : Indian

Age : 23

Sex : Female

Languages known : English(RWS), Tamil(RWS), Telugu(S), DECLARATION

I hereby declare that the information furnished above is true to the best of my knowledge. Place : Coimbatore

Date : (VAISHALY.K)

Contact this candidate