KUNAL A. DOSHI Email:- acqihe@r.postjobfree.com

Contact no:- 961-***-****

EDUCATIONAL QUALIFICATIONS:-

DEGREE

INSTITUTE

UNIVERSITY

AGGREGATE BE in Extc

K. J. Somaiya College of Engineering

University of Mumbai

69.3

H.S.C.

K. J. Somaiya College of Science and Commerce

Board of Maharashtra State

85

S.S.C.

Model English School

Board of Maharashtra State

90.46

SKILL SETS:-

1.Hardware:-

Verilog Hardware Descriptive Language (Basic).

Xilinx Digilent Basys-2 board containing Xilinx's Spartan-3E FPGA and Spartan-3.

2.Software:-

Electric 9.05

LTSPICE

Xilinx ISE Design Suite 14.5

Proteus.

PROJECTS:-

Ripple Carry Adder, Carry Look Ahead Adder and 8x8 SRAM layout design on Electric 9.05 and corner simulation result was observed on LTSPICE.

Adaptive Filter using LMS Algorithm described in Verilog HDL on Xilinx ISE Design Suite 14.5 and implemented on Spartan-3 FPGA.

Digital Designs Barrel Shifter, Candy Vending Machine (FSM), Clock Timer using Verilog implemented on Spartan-3E FPGA.

Theo Jansen’s Mechanism Based Pitch Marking Robot in which robot will mark the ground of sports field using Arduino.

Transistor Tester where the multimeter can measure transistor parameters like NPN/PNP, hfe and hie.

PAPER PRESENTATION:-

Participated in “CONFERENCE ON BIOMEDICAL ENGINEERING”,’PRAKALP’, 2013.

Participated in “IETE”, Technical Paper Presentation on topic “HAZARDS OF ELECTRIC CABLES”, 2012.

CO-CURRICULAR ACTIVITIES:-

Summer Industrial Training in the year 2015.

Back End CMOS Digital VLSI(Basic) in the year 2015.

Front End VLSI (Basic) in the year 2014.

Participated in “VERILOG WORKSHOP” held by IETE held in the year 2012.

EXTRA-CURRICULAR ACTIVITIES:-

Participated in “THE INSTITUTE FOR PROMOTION OF MATHEMATICS EXAM” in the year 2006 and 2007 in VII and VIII grade respectively.

Also participated in State Level SCHOLARSHIP EXAM held in the year 2003 and 2006 in IV and VII grade respectively.

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