Engineering Design

RESUME

S .V.B.Sai Krishna,

S/O S.V.Subba Rao,

Near B.V.S Theater,

D.NO:45-1-141,ongole,

Prakasam (dt),A.P e-mail: acqfyf@r.postjobfree.com

mobile: 973-***-****

Career Objective:

Skilled, resourceful and dynamic individual, seeking challengin g assignment and

responsibility in verification with an opportunity for growth and career advancement as

successful achievements.

Academic Profile:

2012 – 2014 M.Tech. in VLSI Design

Amrita Vishwa Vidyapeetham University, Coimbatore

Amrita School of Engineering, Bangalore CGPA:8.95

2007 – 2011 B.Tech. in Electronics and Communication

Engineering Stream

Jawaharlal Nehru Technological University, Kakinada

SSN Engineering College, Ongole Percentage:70.17

Intermediate in MPC stream,

2005 – 2007

Board of Intermediate, Andhra Pradesh

Sri Chaitnaya junior Kalasala, Ongole Percentage:87

2004 – 2005 SSC

Board of Secondary Education, Andhra Pradesh

Sri Sarada bala kuteer, Ongole Percentage: 79.83

STRENGTH:

Positive Thinking

Punctuality

Thrive In a Team Environment and Work well with Others

SKILL SET:

Programming Skills: C language, Verilog, basics of VHDL and System Verilog

Simulation Tools: H-SPICE, ModelSim, Xilinx ISE, VCS, Virtuoso, Encounter

Technical Skills: Digital Design, VLSI Signal Processing, Computer Architectures, Timing

Analysis, System Verilog

HANDS ON EXPERIENCE:

Worked on Cadence Virtuoso (Spectre/AMS), Encounter.

Worked on simulation tools such as ModelSim, Synopsys Verilog Compiler Simulator

(VCS), Design Complier.

Worked on FPGA kits such as Spartan 2 and Spartan 3e kits using Xilinx tool.

Designing of Analog layout using Cadence Virtuoso and Synopsys Custom Designer.

Worked on Xilinx System Generator using MATLAB

TECHNICAL SKILLS:

Have comprehensive knowledge on the concepts, practices and processes of analog

designing and layout.

Have experience on designing of analog layout for opamp, clock generator, current

mirror, differential amplifiers, capacitor and resistor

Familiar with CAD tools such as various techniques and algorithms used for placements

and routing during Layout Design.

Can program efficiently using Hardware Description languages (HDL) such as VHDL,

Verilog and System Verilog etc.

Familiar with designing of analog designs for basic gates such as NAND, NOR etc using

Cadence Virtuoso.

PROJECT:

TITLE: An Efficient Reconfigurable Architecture for 1-D and 2-D Discrete Wavelet Transform

Insight: Mostly Wavelet Architectures are of Static in nature, if filter length changes the

architectures cannot be reused where as Reconfigurable Architectures are dynami c in nature

and reuses the architecture according to change in filter length .

The Architecture is designed using the fundamentals of Digital Design and Computer

Architectures, simulated in ModelSim and implemented by XILINX ISE, FPGA.

TITLE: FPFA Implementation of Video Graphic Array Display

Insight: This project aimed to establish an interconnection between LCD screen on FPGA

using VGA port to display various colors on LCD monitor. The board used is SPARTAN -3e.

AREA OF INTREST:

Image processing, signal transforms,VLSI architectures and CAD

CO-CURRICULAR ACTIVITIES:

Undergone an industrial training at BSNL in Ongole

Attended workshop on Sentaras structure editor conducted by Synopsys

Attended a workshop on signal and image processing applications conducted by

CORE-EL Technologies

Personal Profile:

Name : S.B.SAI KRISHNA

Father’s Name : SUBBA RAO

Date of Birth : 28-07-1990

Age : 24

Sex : Male

Nationality : Indian

Languages Known : English, Telugu

Marital Status : Single

Alternative e-mail ID : acqfyf@r.postjobfree.com

Declaration

I hereby declare that the information given above is true to the best of my knowledge.

(S.V.B.SAI KRISHNA)

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