Sr. Digital Verification Engineer

RANJITH BIDRI

Design Verification Engineer

Mob :- 997-***-****

Email :- ************@*****.***

Objective

To obtain a Design Verification Engineer position that will utilize my skills and experience in engineering and provide me opportunity to grow and learn.

Experience Summary

Over all experience of 3.0 years in Design verification with MS post graduation in VLSI:

Currently working in Synapse Design Automation as Senior Engineer (Design Verification).

Worked at Whizchip Design Technologies as Intern for 1 year.

Completed MS in VLSI (design & Verification) from Manipal University, Manipal.

Implant training in VLSI front end design and verification VEDA IIT, Hyderabad.

Working for Analog Devices India in UVM based verification from scratch for two of their AMS (MEMS) chips as a Synapse Contractor from last 2+ years.

Worked on a chip starting from developing test plan to GLS sign off.

Experience on development of verification environment for scan simulations on netlist.

Familiar with FuSa verification for automotive products using Synopsys Certitude tool.

Worked on both Block level and SOC level verification.

Developed reference model for DSP (Digital Signal Processing) unit which is tantamount to Cortex M0 based software implementation of the same.

Writing a Paper on "Novel approach for advanced UVM RAL integration".

Good working knowledge of System Verilog and Verilog coding.

Good working knowledge on UVM.

Good debugging skills for which I got appreciation from client managers.

Knowledge on various interfacing protocols like: SPI,AHB, APB,USB3.0,OCP3.0

Awarded with SPOT AWARD for my excellent efforts in consistent, timely and quality deliverable for multiple release of MEMS product.

Skill Set

Simulators: NC-SIM

HDL: Verilog

HVL: System Verilog

Protocol: SPI,AHB,APB,USB3.0,OCP3.0

Methodology UVM

Coverage: IMC

Project Summary

Project- 1: A single axis gyroscope for active safety applications in automotive – For Analog Devices India (UVM Verification from scratch)

Description: This design takes input from gyroscope and acceleration sensors then processed on input data & finally give output data to host processor.

Responsibilities:

Responsibility 1: RAL bring up for verification of System Register File (SRF)

Created base layer for UVM and customized accordingly for reusability of RAL across the projects.

Wrote wrapper functions around the built in RAL functions for more reliable and readability purpose.

Developed and integrated RAL Adopter, Predictor and Bus monitor for data update and access between RAL & DUT in accordance with the bus protocol.

Prepared test plan and developed test cases for verifying SRF.

Code and function coverage closer.

Responsibility 2: Verification of SPI bus protocol at SOC level

Prepared Test Plan for verifying the SPI scenarios at SOC level.

Developed UVM components and objects for data generation and driving on to bus interface.

Developed Scoreboard for auto check on response frames from DUT.

Coded assertions for protocol checking.

Listed and coded cover points for coverage.

Code and function coverage closer.

Responsibility 3: Verification of Non-volatile Memory (OTP)

Prepared Test Plan for verifying the NVM scenarios at SOC level.

Developed reference model (NVM control block) for verifying OTP and Refreshing.

Developed CRC computation function for randomized NVM data and backdoor corruption options provided for test writer.

BIST functionality verification.

Listed and coded cover points for coverage.

Code and function coverage closer.

Responsibility 4: MISC

Assertions for verifying glitches on derived clocks in design.

Developed checker for Analog-Digital connectivity signals.

Worked on GLS and signed off successfully.

Project- 2: A three axis MEMS accelerometer for Health monitoring applications in Medical Equipments – For Analog Devices India (UVM Verification from scratch)

Description: This design takes input from accelerometer sensors then processed on input data & finally give output data to host processor.

Responsibilities:

Responsibility 1: Cortex M0 software based DSP unit verification

Developed UVM components and objects for sensor data generation and driving the same on to analog behavioral module.

Developed reference model which is tenement to Cortex M0 software based implementation.

Developed AHB bus monitor to snoop sensor data and address for checkers and reference model.

Verified 3rd order IIR filter by plotting the filter response on Bode plot.

Prepared Test Plan for verifying the various scenarios.

Code and function coverage closer.

Responsibility 2: Verification of CRC Engine at block level

Verified at block level using UVM verification environment.

Developed Scoreboard for CRC checking.

Coded assertions for APB bus protocol checking.

Stitched up assertions at SOC level environment.

Listed and coded cover points for coverage.

Code and function coverage closer.

Responsibility 3: ECC verification for Fuse Memory (OTP)

Responsible for creating test plan and implementing verification.

Developed reference model and test cases.

Verification of all fuse memory related features.

Code and function coverage closer and writing test case for hitting holes.

Responsibility 4: MISC

Developed assertions for AHB and APB protocol checking.

Took whole responsibility for GLS and signed off successfully.

Developed a verification setup for scan chain verification on gates.

Verified Functional Safety Scenarios using Synopsys Certitude tool.

Project- 3: OCP3.0 VIP Development

Description: Development of OCP Monitor UVC using System Verilog and UVM methodology. Stitching up of all the components and objects to verification environment.

Role and Responsibility:

The aim of this project was to understand UVM concepts.

Developed OCP3.0 Monitor UVC supporting Basic & Burst operations

Project- 4: Design & Delivery of Monitoring System for MAC & PHY layer in USB3.0 VIP (Using System Verilog, Internship Project)

Description: Data, Status and Command signals from the PHY Layer are sent to the monitor block where signal checking, CRC checking and validation of various packets is done. Driver block gets these signals from monitor block through mailboxes. User is provided with an access to inject error to various packets in driver block and these error injected packets are then sent to MAC layer of USB3.0.

Role and Responsibility:

Development of Monitor component for monitoring the link training sequences.

Development of Driver for error injection.

Development of checker for transactions between MAC & PHY layer using System Verilog

Project- 4: Packet Router test environment development using System Verilog.

Description: Project is to understand System Verilog concepts. This is a simple packet router which has an input port and three o/p ports. The incoming packet is routed to one of the three o/p ports depending on the packet header.

Role and Responsibility: Developed Test Plan & full verification environment in System Verilog.

Education

Year

Degree

Major Subject

University

Marks

2012

MS

VLSI

Manipal University, Manipal

8.6 CGPA

2009

BE

E&C

VTU, Belgaum

64 %

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