Lin Zhong

*** ******** ***. #***, *** Jose, CA **126

Ph: 510-***-**** (h), 510-***-**** (c) Email: acqetj@r.postjobfree.com

Objective

Work toward a creative and challenging career as a communication system engineer in the wireless

communication industry.

Summary of Technical Skills

Solid Wireless Communication, DSP and video processing background, with extensive hands-on

experience for development on a variety of programmable/reconfigurable platforms

Knowledgeable in different wireless communication and video standards and technologies, such

as digital front-end (DFE) signal processing, CDMA and OFDM baseband signal processing,

H.264, MPEG decoder algorithms. Skillful in different design tools such as Matlab, Simulink,

SPW, C, asm, and quick prototype tools including Altera’s Quartus II tool chain, DSP Builder

design flow, and Nios II embedded processor flow etc. Good communicator, with contribution to

the hardware and software teams on developing company’s hardware architecture and improving

software design flow. Managed and mentored the application team in startup environments. Led

and worked with offshore outsourcing team to improve development efficiency.

Relevant Professional Experiences

Engineer/Manager/Director for Application Engineering group in Element CXI, San Jose, CA.

(03/2005~current)

DFE related work

Recent FPGA related:

• Designed and delivered a digital front-end (DFE) matlab/simulink reference model for

company’s Intel DFE IP project.

• Designed and implemented a DUC/DDC/CFR, and DPD feedback accelerators using

Altera’s DSP Builder approach and verified it on Altera FPGA board, and tested the

performance on ADI’s MS-DPD platform.

• Developed and tested different DUC models and tested on several RF DAC board to

support a highly flexible SDR design. Designed a high rate parallel FIR with DSP builder

for FPGA test.

• Tested and figured out the usage of ADI’s MS-DPD platform, ADI’s RF-DAC board, and

Maxim RF-DAC board. Trained and mentored team members to use the platform.

• Figured out problem and solution to support DPD development

Earlier work on DFE mapping to company’s internal reconfigurable architecture:

• Developed technical approach based on their technical requirements of external demo

and evaluation such as for Huawei, TI/GreyChip, Maxim etc, and potential company’s

competitors. Estimated computation complexity and algorithm paper mapping to our

architecture. Paper mapping several of these small projects such as CRC, DAGC, DPD

forward path, parallel FIR, turbo, high rate Viterbi, etc. and with some implementation

for the purpose of demostration and benchmark comparison.

• Developed CIC filter for GSM DDC, mentored other team members for an efficient

implementation of a multi channel filters and NCO using our unique features of the

reconfigurable architecture.

• Led the team to finish implementation of DUC/DDC/CFR/DPD (LMS based) on Helium

Architecture, as our initial DFE solution, and verified on our 2nd generation RTL

simulator

• Implemented a FFT based CFR model in SPW, a clip and filter CFR model in ADS.

• Investigated several CFR approaches to evaluate which method better fit for our DFE

solution.

Baseband related work:

LTE/Wimax baseband related:

• Comprehend LTE Physical layer standards and finished a paper mapping to evaluate

resource requirements and provided architecture enhancement suggestions.

• Finished a Turbo encoder and decoder paper mapping analysis for hardware resource

estimate and architecture enhancement suggestion. Implemented a SISO decoder on our

software tool chain to verify the turbo decoder paper mapping.

• Completed a LDPC encoder and decoder paper mapping analysis for hardware resource

estimate and architecture enhancement suggestion. Implemented them on a newly-

developed architecture evaluation software as part of the software test as well as

hardware enhancement justification.

• Investigated several MIMO algorithms for MIMO detection, finished a paper mapping

for a sphere decoder for resource estimation.

ISDBT/DVB baseband related:

• Led a team to finish the ISDBT receiver processing chain project on our first generation

chip (code named Hydrogen)/development board.

• Implemented a Viterbi decoder on our Hydrogen chip.

• Wrote Matlab code and provided reference test vector to support Reed-Solomon decoder

implementation and debugging effort.

• Developed a SPW reference model and provided test vector to support the ISDBT

receiver implementation and debugging effort.

• Guided team members on the implementation/debuging of FFT, implemented some part

of the FFT on our Hydrogen chip. Trained new graduates to use company’s architecture

and tool chain. Supervised them to implement QPSK/QAM16/QAM64 demodulation and

deinterleaver. Implemented a deinterleaver as an example.

MPEG4/H.264 related:

• Created paper mapping for a H.264 decoder. Implemented a few heavy duty processing

functions using a tcl based instruction simulator: deblocking filter, intra prediction, inter

prediction, integer transform, support mapping and debugging for cavld

• Implemented MPEG4/IDCT in SPW based design flow for our jointed tool development

(w/ Coware)

• Developed SPW based element processing library for software team.

• Early stage systemC development for IDCT.

Miscellaneous projects and architecture/tool development and evaluation related:

• Finished an AES mapping and implementation with tcl based tool on Hydrogen chip.

• Developed a few video fun game demo systems for the initial tape out chip and

demonstrated it in JCES/w Toyota.

• Completed a paper mapping for SNOW3G encryption/decryption for resource estimate.

• Finished some image processing functions for the initial TI evaluation such as sobel edge

detector, mediam filter and sad, and guided our group members for implementation.

• Guided beam forming mapping and implementation for further TI evaluation.

Sr. Member of Technical Staff, QuickSilver Technology (07/2001 – 11/2004)

WiFi (802.11a/b/g) related work

Project manager and technical lead on 802.11a system development on the reconfigurable

Adaptive Computing Machine (ACM) platform - Led the design and development efforts

of porting an 802.11a system on QST’s novel programmable adaptive distributed

dataflow processing IC. Efforts included working with the customer to define the

requirements of the project as well as led the overseas outsource firm to develop the

above system.

• 802.11a Rx and MAC development on the reconfigurable ACM - Conducted 802.11a Rx

and MAC algorithm mapping and partition. Developed the key 802.11a Rx and MAC

layer modules such as Viterbit decoder, CRC etc. Testing, benchmarking, and debugging

of the entire system on simulated environment as well as on the IC development board.

Characterized system performance with lab instrumentation such as logic analyzers etc.

Engaged other activities such as ACM’s software tool testing and debugging, explanation

of the system requirements and hardware architecture to people in different groups.

• 802.11a Tx development on the reconfigurable ACM (Adaptive Computing Machine).

Strong experience with ACM architecture and programming, contributed to tools and

architecture development of reconfigurable bit-manipulation node processor, developed

802.11a Tx simulation models, conducted algorithm mapping and partition analysis,

develop various software modules using Simulink, C, ASM-C, ASM language, for bit

exact simulation, testing, and execution on an FPGA IC emulation board. These modules

and codes were used in the FPGA board demo as part of the project delivery. Also other

miscellaneous supporting efforts such as jpeg demo development, etc.

WCDMA related work

• WCDMA and 802.11a algorithm analysis and simulation model development - Analyzed

different algorithm “hot spots” in WCDMA, 802.11a, their implementation options, and

their requirements on the new ACM architecture. Build simulation models to verify

algorithm and system performance.

• CDMA rake receiver development on the reconfigurable ACM (Adaptive Computing

Machine) – Became an expert in ACM architecture and programming, developed CDMA

simulation model, conducted algorithm mapping and partition analysis, developed

different software modules using C, Qasm and WIFF (an ACM assembly languages), bit-

exact co-simulation, debugged on FPGA and prototype IC development board, converted

Simulink code to C based host code for demonstration, analyzed and improved

performance of the Rake finger demo system. The results were demonstrated and

recognized on 2002 CES show in Las Vegas.

System Design Engineer, Philips Semiconductors (01/1998-05/2001):

CDMA-IS95/CDMA2000/WCDMA related work

• Followed the 1xEV-DV standards development. Created a system evaluation model -

Tracked technical discussions of the latest 1xEV-DV standards development from

different companies. Developed a Matlab system evaluation model based on the

Strawman document specified by the standards committee.

• IS-95 chip/firmware testing- Participated in lab work and the handset prototype system

testing. Conducted modem portion of chip/firmware testing.

• IS-2000 downlink model development and simulation-Developed a combiner model,

modified SIR measurement model and turbo code model, and integrated these blocks

into a system downlink model, conducted downlink performance simulations and tuning

of the system.

• IS-95 downlink model development and simulation, algorithms development and

simulation - This included AGC floating and fixed point algorithm development, AFC

algorithm model debug, and integration of these two models into an existing downlink

model. Rewrote several custom coded blocks and converted the downlink SPW model

into a faster CGS platform. With this newly developed model, the first downlink system

performance was achieved in our system group, and was used in the later algorithm

study, system parameter tuning and performance evaluation phases of the project.

Degradation of the downlink model from various blocks was also studied.

Education

MSc. in Telecommunication, University of Saskatchewan, Saskatchewan, Canada.

Thesis: System design of a TDD-CDMA fixed wireless data network

PhD. in Space Physics, Center for Space Science and Applied Research, Chinese

Academy of Sciences,

MS in Radio Physics, Wuhan University, China

BS in Radio Electronics, Wuhan University, China

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