Project Design
Resume:
To acquire a challenging career with a solid company utilizing the opportunity to offer proven and developing skills within the company.
Seeking an internship position in the field of VLSI design, with the opportunity to work on projects from conception to completion.
Degree
Board / University
Year
CGPA/ Percentage
M.Tech
VIT University
2016
7.2
B.Tech
AVS College of Engineering and Technology, JNTU Anantapur.
2014
71.48
Intermediate
Board of Intermediate Education, Andhra Pradesh.
2010
90.1
S.S.C
Board of Secondary Education, Andhra Pradesh.
2008
84.4
EDA Tools
- Modelsim, Xilinx, Cadence, TCAD
Hardware Description Languages
- Verilog, HDL
Software Skills
- perl, basics of C
Platforms
- Windows
Architectures
- µP 8086
Hardware Expertise
- Altera FPGA Board
Mathematical Tools
- Matlab
Received “PRATIBHA PURASKAR” scholarship for two times.
Participated in National Level Technical Symposium’s.
Leader in managing team for the national level technical feast conducted by our department in the college.
Dec-2013 -
Project Name
VLSI design of 32 bit RISC processor core using VHDL
Mar-2014
Team size
5
Role
Leader
Roles performed
Involved in understanding the design flow of RISC processor.
Involved in understanding the various interfaces.
Involved in resolving the errors arose in coding.
Technology used in project
Operating System
Windows 7
Tools
Xilinx, Modelsim
Programming Language
VHDL
Description
Designed a CPU based on the insight that a simplified instruction set provides higher performance when combined with a microprocessor architecture capable of executing those instructions using fewer microprocessor cycles per instruction.
Project Name
Design and Analysis Of Dual Material Double Gate Tunnel FET
Duration
July 2014 – Dec 2014
Tools Used
TCAD
Description
DM-DGFET is designed and comparison between Dual Material Single Gate TFET and DM-DGFET is made interms of energy band diagrams, I-V characteristics. Dual Material Double Gate Tunnel FET is used to boost up the ON Current and hence from the results Dual Material Double Gate Tunnel Field Effect Transistor would be an excellent contender to replace the presently used conventional CMOS technology.
Project #1
Project #2
Project Name
Design and Analysis of 5T SRAM Cell For Low Leakage Current
Duration
Jan 2015 –May 2015
Tools Used
Cadence Virtuoso
Description
A 5T and 6T SRAM Cell is designed in frontend and as well as backend in CMOS of 180nmTechnology and frontend design for FinFET of 45nm Technology. Different low power techniques were applied and analyzed the leakage currents. The 5-transistor (5T) bitcell that uses sizing asymmetry to improve read stability and also investigated single-ended sensing for the 5T SRAM cell.
I have the ability to update myself according to the environment.
Responsible, Good Listener.
Hardworking, sincere & diligent.
Playing chess, Surfing Internet.
Watching TV, listening to radio.
Name
Agineti Ashok
Birth Date
07 June 1992
Residence
7-33, Mogilivaripalli village, Mittoor Post, Bangarupalyem Mandal, Chittoor, Andhra Pradesh, 517429.
Nationality
Indian
Marital Status
Single
Gender
Male
Passport Details
Number
L8252801
Issue Date
25/032014
Expiration Date
24/03/2024
Country
India
Language
Speak
Read
Write
English
Fluent
Fluent
Fluent
Telugu
Fluent
Fluent
Fluent
Hindi
Basic
Basic
Basic
Present Address
Agineti Ashok, VIT University (Chennai Campus), Reg No: 14MVD1001, Vandalur-Kelambakkam Road, Chennai, Tamil Nadu, Pin code: 600127.
Mobile
***************@*****.***
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