VLSI Engineer

RESUME

SWETA S. BHURSE

Nisheetha PG Hostel No **,R J garden, Mobile no.:-989*******

Anand nagar, opposite to kalamandir, ******.*****@*****.*** Back side of dominos pizza, marathahalli,

Bangalore-560037

OBJECTIVE:-

To work in a professional environment where i can explore and implement my skills and talent for the growth of the organization and also which will help me for my personal development. EDUCATION:-

Completed MTech in VLSI Design from Electronics and communication Department centre for VLSI and Nanotechnology of Visvesvaraya National Institute of Technology(VNIT), Nagpur. Examination College- Year of passing Percentage/

University CGPA

MTech VNIT, Nagpur SUMMER 2015 8.62

BE(Electronics and KITS,Ramtek SUMMER 2012 80.01%

Communation) RTMNU

HSC (CBSE) JNV Talodhi(Ba.) SUMMER 2008 89.60%

SSC (CBSE) JNV Talodhi(Ba.) SUMMER 2006 90.80%

PROJECT:-

BE:- “Subpower Allocation in OFDMA”.

Description:- We studied how to distribute power and bits among the subcarriers in Orthogonal Frequency Division Multiple Access(OFDMA) system. OFDMA is a multiple access scheme that provides multiplexing operation of data streams for multiple users onto downlink and uplink sub- channels. We studied different algorithms used for sub power allocation in an OFDMA system. The power is distributed to each subcarrier in OFDMA system. MTech:- “Process Simulation of various Gate Lengths Bulk FinFETs”. Description:- The FINFETs are likely to replace classical MOSFETs as active device in most of the circuits at low dimension regime. Although the unit process steps are same for these devices, process integration issues varies because of three dimensional structure of FINFETs. The process simulation schemes for various gate length such as 22nm, 14nm, 10nm and 7nm FinFETs on bulk Si substrate are studied, from the viewpoints of device size scalability and short channel effect control. The impact of major device parameters like performance of all gate length 3D Bulk FinFETs are analyzed with synopsys Sentaurus TCAD simulations. The importance of silicidation method is studied and its impact on various electrical parameters values is inspected. Attempts are also made to inspect the variation of device performance parameters with respect to fin width, fin length, gate oxide thickness and S/D doping concentration. TECHNICAL SKILLS:-

Operating system:- Linux, Windows7.

Language:- C, VHDL, Verilog.

Software:- Sentaurus TCAD, Cadence, Mentor graphics Eldo, Modelsim/Xilinx, NgSpice, Comsol4.3a, Matlab.

PUBLICATIONS:-

1. Ankush Nikam, Swati Salunke and Sweta Bhurse(2015,March). Design and Implementation of 32bit Complex Multiplier using Vedic Algorithm, in International Journal of Engineering Research and Technology,2015,ISSN:2278-0181,Vol.4

TITLE:-

Awarded “Best outgoing student” from batch -2012 in KITS, Ramtek. Academics

1. 7

th

university topper in BE degree.

2. 4

th

university topper in 6

th

semester.

3. 1

st

university topper in 4

th

semester.

4. 7

th

university topper in 1

st

year.

Sports

1. Winner in volley ball at cluster level held at Wardha and Gadchiroli. EXTRA-CURRICULAR ACTIVITIES:-

1. Participated in National level paper presentation organized by B.D College of Engineering, Wardha and IGPCE, Nagpur.

2. Attended INUP Familiarization workshop held at IIT Bombay from 26-28may,2014. STRENGTHS:-

1. Hardworking.

2. Ability to work with and manage others.

3. Punctuality.

HOBBIES:-

1. Playing Volley ball.

2. Drawing Rangoli.

PERSONAL DETAILS:-

Father’s Name:- Shamrao N. Bhurse.

Date of Birth:- 13/07/1990.

Gender:- Female.

Nationality:- Indian.

Permanent Address:- Mul, Near Charkha Sangh, Ward No.-15,Dist:- Chandrapur, Maharashtra. DECLARATION:-

I hereby declare that information given by me is correct and true to the best of my knowledge. Place:- Bangalore SWETA S. BHURSE

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