RTL design,vhdl,verilog,Analog design

CAREER OBJECTIVE

To use my existing skills and knowledge to gain experience in VLSI industry and keep updating myself with newer technologies so as to achieve higher benchmarks in this field. ACADEMIC CREDENTIALS

Qualification

Institute

Board/University Year Percentage

M.Tech. (VLSI VNIT, Nagpur

VNIT, Nagpur 2013-2015 8.62(CGPA)

Design)

B.E (Electronics SVPM’s Coe,Baramati

Pune University 2008-2012 61%

Engineering)

Higher Secondary Mahtmaphule College,

Latur board 2007 61.83%

(XII) Ahamadpur, Dist-Latur

Secondary (X)

Yeshwant Vidyalaya,

Latur board 2005 70.13%

Ahamadpur Dist-Latur

PROJECTS

Spectral estimation of signal using MUSIC Algorithm): Duration – 1 Year

FPGA Based Fully Configurable Digital Clock: Duration – 2 weeks (1st Year M.Tech.)

Gesture Recognition by using color identification: Duration-2 week (3rd year Undergrad)

FPGA Based Up-Down Counter (Mini Project): Duration – 2 Weeks (3rd Year Undergrad)

Radio transmitter: Duration – 2 Weeks (3rd Year Undergrad) SEMINARS AND WORKSHOPS

Semiconductor thin film deposition: Techniques, Processes and Equipment Design (By Dr. Nitin Kale, Chief Technology Officer, Nanosniff Technologies, IIT Bombay)

Seminar Series: Nanoelectronics (Prof. Kaushik Roy, Edward G. Tiedemann Jr. Distinguished Professor, Purdue University USA) (March 2014)

o Nano-electronics: A bottom up approach to system design o Spintronics and magnetics: Prospects of ultralow power on-chip logic and memory

Introduction to VLSI design Flow (Vaibhav Gokhale, Application Engineer at Atoptech, Santa Clara, USA) (Jan 2014)

SOFTWARE SKILLSET

Specialized tools: Cadence Virtuoso, Mentor Graphics, Sentaurus TCAD, Xilinx ISE, MATLAB.

Programming Languages: C, VLSI Hardware Description Language(VHDL),Verilog

Operating Systems: Windows XP/Vista/7/8, Linux Ubuntu 14.04, CentOS 6, Red Hat 5

Other office tools: Microsoft Office Word, Microsoft Office Excel, Microsoft Office Power Point Present Address:

Sri Lakshmi PG (formerly Rest In PG),

#84,Vibgyor School Road, Beside Sri Rama

Samrudhi Apartment Near Kundalahalli

Gate,Bangalore-560066

Gopal Sanjay Ledange

M.Tech., VLSI Design

Contact No. : - +919*********

E-mail:- ****************@*****.***

SEMINARS PRESENTED

Academic

“Fabrication of Quantum Dots by LPCVD”

“Capacitive Pressure Sensor”

ACHIEVEMENTS

All India Rank 1441 (99.36 Percentile) among 2,56,000 ECE Students in GATE 2013 PERSONAL DETAILS

Father’s Name :- Sanjay Ledange

Permanent Address :- At-Kalmula, Pq-Kawalgaon, Tal-Purna Dist-Parbhani-431511

Date of Birth :- 17stJuly 1990

Language Known :- English, Hindi, Marathi.

Marital Status :- Unmarried

Nationality/Religion :- Indian

Interest & Hobbies :- Listening music, Playing Cricket, swimming DECLARATION

I do hereby declare that the above information is true to the best of my knowledge. Place: Bangalore Gopal S Ledange

Date: 10th Aug 2015 (Signature)

Contact this candidate