Analog design

EXPERIENCE DETAILS

Position : VLSI Engineer-Analog

Company : Mirror Technologies Private Limited, Chennai

Duration : May 2014 to till date (1+ Years)

CAREER SUMMARY

1+ Years of Experience on Analog Design based Products

Working in PLL, Frequency Divider,Comparator,Level Shifters, ADC based applications

Having very good knowledge, practice and experience in CMOS technology

Design, develop and prototype Analog and mixed signal VLSI systems.

Use Hardware Description Languages to design cores and standalone logic.

Have implemented and exposure with Xilinx FPGA Spartan6

Assisted in development of RTL designs to meet performance goals.

Basic knowledge about Static Timing Analysis, CTS, Layout Design, Floor Planning and Routing

Basic knowledge in C,C++

TECHNICAL PROFICIENCY

HDL Languages - Verilog, VHDL, System Verilog HDL

EDA Tools - Mentor Tanner AMS, PSpice, HSpice, Cadence Virtuoso

Implementation - XILINX-Chipscope, FPGA Spartan 6

Simulation - ModelSim, Isimulator

Operating systems - Windows, Linux

Layout - MicroWind, L-Edit

Circuit Design - NI Instruments-MultiSim

ACADEMIC RECORD

M.E. Applied Electronics from Sri Venkateswara College of Engineering, Anna University, Chennai With First Class 84.40%,2014.

B.E. Electronics & Communication Engineering from Thanthai Periyar Government Institute of Technology,Anna University,Chennai with First Class-71.90%,2012.

Higher Secondary from Bharathidhasanar MHSS, Arakkonam with aggregate 92.58%,2008.

Matriculation from Dr.VGN MHSS, Tiruttani with aggregate 81.00%,2006.

PROJECTS HANDLED

5. Single-Phase Clock Multiband Flexible Divider

EDA Tool : Mentor Graphics-Tanner Tool

Simulation : ModelSim-Verilog.

Divider Block’s : Wide band MultiModulus Prescaler, Programmable Counter, Swallow Counter

CMOS Technology : 90nm

My Role : Analog Designer

Team Size : 3

Description:

Divider divide the frequencies in the three bands of 2.4–2.484 GHz, 5.15–5.35 GHz, and 5.725–5.825 GHz with a resolution selectable from 1 to 25 MHz..

The wideband single-phase clock 2/3 prescaler used in this design which consists of two D-flip-flops and two NOR gates.

Wideband multimodulus prescaler which can divide the input frequency by 32, 33, 47, and 48.

The 6-bit counter consists of six asynchronous loadable bit-cells, a NOR-embedded DFF and additional logic gates to allow it to be programmable from 0 to 31 for low-frequency band and from 0 to 47 for the high-frequency band.

The programmable counter is a 7-bit asynchronous down counter which consists of 7 loadable bit-cells and additional logic gates.

4. Phase Locked Loop IC

EDA Tool : Mentor Graphics-Tanner Tool

Application : Frequency synthesizer Applications

IC Block’s : PFD,Loop Filter,VCO

CMOS Technology : 180nm

My Role : Analog Designer

Team Size : 3

Description:

A phase-locked loop or phase locked loop is a control system that generates an output signal whose phase is related to the phase of an input signal.Output frequency range is 50-100MHz.

Phase detector compares between input and DCO output signal. Output depends upon the phase error. Output signal contains low frequency and higher frequency component.

Loop filter is simply act as a integrator.

Voltage Controlled Oscillator is treated as a linear, time-invariant system. Excess phase of the VCO is the system output.

3. CMOS High-Voltage Transmitter IC

EDA Tool : Mentor Graphics-Tanner Tool

Application : Ultrasound Medical Imaging Applications

IC Block’s : Level shifters, Output Driver

CMOS Technology : 180nm

My Role : Analog Designer

Team Size : 3

Description:

The architecture consists of a level shifter, which converts the external digital-signal processor/field-programmable-gate-array generated 1.8Vp p input trigger signal to a 5Vp p pulse signal.

The 5-Vp p signal is divided into two separate paths. The upper path contains a second level shifter and a tapered buffer to convert the signal to swing between 5 and 10 V in order to drive the gate of the PMOS transistor of the output driver.

The key part in the transmitter chain is the push–pull output driver, which excites the following CMUT with a HV pulse signal to produce a large acoustic pressure signal.

10 Vp p pulse signal results at the output of the driver with small delay.

2. FM0/Manchester Encoding

EDA Tool : Mentor Graphics-Tanner Tool

Simulation : ModelSim-Verilog

Application : DSRC Applications

IC Block’s : Gates,Flipflops, Multiplexers.

CMOS Technology : 180nm

My Role : RTL Designer

Team Size : 3

Description:

The Manchester encoding is realized with a XOR operation for CLK and data. The clock always has a transition within one cycle.

Design adopts the CMOS inverter and the gated inverter as the switch to construct Manchester encoder.

Finite State Machine of FM0 code is classified into four states. A state code is individually assigned to each state, and each state code consists of A and B.

FM0 encoding depends not only on the data but also on the previous-state of the FM0 code.

The purposes of FM0 and Manchester codes can provide the transmitted signal with dc balance.

1. Low-Voltage Low-Power Double-Tail Comparator

EDA Tool : Mentor Graphics-Tanner Tool

Application : ADC Applications

Layout : Microwind

CMOS Technology : 180nm

My Role : Analog Designer

Team Size : 2

Description:

Comparator is one of the fundamental building blocks in most analog-to-digital converters (ADCs).

Double-tail dynamic comparator is designed so that the latch delay time is profoundly reduced.

The double tail enables both a large current in the latching stage and wider tail transistor, for fast latching independent of the input common-mode voltage and a small current in the input stage for low offset.

This is implemented using 180nm CMOS technology in 1.8 supply Voltage.

FOR PRACTICE

Efficient Carry Select Adder using carry generation unit

SRAM Design using MultiBit-Flipflops

Power gated logic using ECRL

Floating point Three Term Addder

Design of Ring Oscillator in 90nm CMOS Technology

Pseudo Chaotic Sequence(PCS) Generator for Security Applications

CCSDS Lossless Data Compression

Dual edge triggered FlipFlops

MINI PROJECTS

Performance Analysis of All Digital Phase Locked Loop(ADPLL)

Improved Matrix Multiplier Algorithm for DSP Applications

PUBLICATIONS

” Analysis of ADPLL Design Parameters using Xilinx”, National Conference on Modern Electronics and Signal processing’14 held in Velammal College of Engineering, Chennai.

” Analysis of ADPLL Design Parameters using Tanner Tool”, International Journal of Advanced Research in Electronics and Communication Engineering (IJARECE) Volume 3,Issue 4, April 2014.

ACHIEVEMENTS

Qualified GATE 2014 Score Card

University Rank Holder

Centum in Mathematics in Higher Secondary

Awards in Quiz Competitions

PERSONAL SKILLS

Self Motivation

Adaptable to any Environment

Planning and Prioritizing work

Hard Worker

HOBBIES

Surfing New Technologies in VLSI

Reading Books

Solving interesting Puzzles

Playing Mind Games

PERSONAL PROFILE

Name : M.T.Anbarasu

Father’s name : M.K.Thiyagarajan

Mother’s name : P.GnanaSelvi

Date of birth : 24th November 1991

Languages known : English, Tamil & Telugu

Sex : Male

Marital Status : Single

Nationality : Indian

Permanent Address : 4,Kalaimagal Street, Anna Nagar

Chittoor Road,Tiruttani,Tiruvallur(D.t) – 631209

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