Looking for internship.My skill set:Verilog,System Verilog,UVM..

Snehalata Basavaraj Patil

Mobile: +91-974*******

E Mail: *************@*****.***

Objective

To work in an organization, develop various skills which would enable me to grow while fulfilling organizational goals.

Academic Profile

Title Name of the Institute University Duration Marks B.E KLES College of

Engineering and

Technology Belgaum

Visvesvaraya

Technological

University (VTU),

Belgaum Karnataka

2008-

2012

79.6%

M.Tech(2nd-

sem)

Visvesvaraya

Technological University,

Belgaum Karnataka

Visvesvaraya

Technological

University (VTU),

Belgaum Karnataka

2014-Till

date(2nd

sem)

72%

Technical Skill- Summary

HDL/HVL : Verilog, System Verilog

Simulation/Synthesis Tools : Modelsim, Aldec Riviera Pro, XILINX ISE 12.1E Programming language : C, C++

OS platforms : Windows

Protocols : AMBA APB, AHB

Work Experience-Summary

Period

Organization Designation

Dec 2012 – Dec 2014

TATA Consultancy Services Systems Engineer

Trainings Attended/ Certifications

3 months Initial Learning Program by Tata Consultancy Services on C++, Unix and Embedded Systems.

2 months training on RTL Design.

2 months training on IC Layout Design,Physical Verification and Standard Cell Library.

Work Experience-Detail

Company: TATA Consultancy Services - Bangalore

Project 4: Development of AMBA APB Slave UVC using SV based UVM Methodology

Description The project involves the development of APB Slave UVC. The developed APB Slave UVC can be used to verify APB Master. Roles and

Responsibilities

Understanding the specifications of AMBA APB.

Planning the tests, assertions, & coverages.

Developing tests, assertions and functional coverage.

Developing the Driver logic.

Simulation & Debugging.

Duration 3 months

Team Size 5

Tools Aldec Riviera Pro 2013.06

Project 3: VIP Development: Development of Synchronous Dual Port RAM VIP Using SV based UVM Methodology

Description

The project involves the development of VIP for dual port synchronous RAM DUT having UVC's such as sequencer, driver, monitor, agent and scoreboard.

Roles and

Responsibilities

Understanding the specifications of synchronous dual port RAM.

Developing the test plan and verification plan.

Developing the verification environment.

Writing assertions and coverage.

Debugging the test environment.

Duration 2 months

Team Size 5

Tools Aldec Riviera Pro 2013.06

Project 2: VIP Development: Development of Synchronous Arbiter VIP Using SV

Description

The project involves the development of VIP for synchronous arbiter DUT with System Verilog verification components such as transactor, generator, driver, mailbox and monitor. Roles and

Responsibilities

Understanding the specifications of synchronous Arbiter

Developing the verification environment

Developing generator and driver

Duration 2 months

Team Size

5

Tool Aldec Riviera Pro 2013.06

Project 1: IP Development: Development of Synchronous FIFO IP using Verilog

Description

The project involves the development of synchronous FIFO which stores the data in consecutive memory locations until it gets full and retrieves the data from the memory locations in first-in first-out fashion until it gets empty based on write and read enable signals.

Roles and

Responsibilities

Understanding the specifications of synchronous FIFO

RTL coding of synchronous FIFO in Verilog

Verification of the RTL code using Verilog testbench. Duration 1 month

Team Size 1

Tools Aldec Riviera Pro 2013.06

Academic Project Details:

Project 1:

Project in Final year

B.E

Design and implementation of Zigbee based wireless voice to text translator in hospitals/airlines assistant system for blinds/illiterates.

Period 12-2011 to 04-2012

Description This Project is intended to help and support people with disabilities such as blinds and deaf. Voice to Text translator acts as way of communication providing opportunities to work in organizations using their voice.

In this project voice is input to the system. The system is first trained with predefined words and when speaker speaks into the system the words are compared and displayed on the LCD. Due to high range we have implemented using zigbee wireless technology. Voice to text translator is highly time-saving, user friendly and can be implemented in any language. Very useful for people with disabilities, for controlling appliances. Finds application in many fields such as military, medical, airports, hospitals etc.

Team Size 3

Duration 5 months

Role Requirement Analysis & Design Implementation using IC HM2007 and 8052 microcontroller

Language Embedded C

Personal Details

Date of Birth : 16th April 1991

Address for Correspondence : Plot 660, 2nd stage R.C Nagar Belgaum. Karnataka. (India)

I would appreciate the opportunity to discuss how I might further contribute to your organization.

I look forward to hear from you.

Sincerely,

Snehalata Basavaraj Patil

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