Assistant Engineer

Vijaykumar Madiwalar

#***, *** *****, ********** *****, 21st main

Vijaynagar, Bangaluru-40

( : +91-809*******

* : *****.*********@*****.***

EDUCATION

Program/Course Institution %/CGPA Year of completion MS/Microelectronics IIT Madras, Chennai 8.4 June 2015 BE/ECE SJCE, Mysore 81 2008

XII JSS College, Dharwad 88 2004

Karnataka CET 2004 rank=207 and GATE 2011 score=728, AIR 564. WORK EXPERIENCE

Software Engineer at SoftJin Technologies. 2008-2010

Implemented the digital blocks using Verilog HDL and verified on FPGA.

Developed software routines to transfer data between FPGA and system using C.

Developed test regression setups using TCL and Perl scripts. Teaching Assistant at IITM, Chennai. 2011-2014

Worked as teaching assistant for the courses Digital Design and Networks & Systems. SKILLS

Skills : Digital design using Verilog, understanding of STA and scripting. Languages : Verilog, C, Python, Matlab, Shell scripting, TCL. Software : Xilinx ISE, Synopsys design compiler, LATEX, HSPICE. Experience in Design and Verification

Designed and verified the serial communication IPs RS-232 and SPI in verilog HDL. Serial communication from FPGA to PC is tested on FPGA board. System calls written in C are used to send and receive the data at the PC side.

An arbiter is designed using verilog HDL which acts as interface between serial interface and video encoder in FPGA and it is verified on FPGA board.

During the course work, designed and verified algorithm for finding Hadamard transform in verilog HDL. Tested on FPGA board.

Designed an asynchronous FIFO using Verilog HDL. Experience in scripting

Created the regression setup to test the place and route tool using TCL. Script picks up test cases in the folder, runs the tool, check the log and gives the result. This helped us to test the tool very effectively on every release of the tool.

SSTA algorithms to find the circuit delay of digital circuits implemented. Python code reads the digital circuit, populates the data and performs forward SSTA to find the circuit delay. MS Courses

Digital IC design

Logic design

CAD for VLSI (Front end)

DSP architecture and Embedded systems

Computer methods in elec engg

Math methods and algos in signal

processing

MS THESIS

Thesis involves Statistical Static Timing Analysis (SSTA) on digital circuits with the proposed skew-canonical delay model, which has results with same accuracy as quadratic delay models with a marginal computational overhead compared to conventional linear SSTA. SSTA algorithms were implemented using the Python language and verified on ISCAS85 benchmark circuits against Monte- Carlo simulations.

This work was presented in DATE 2014 as a research paper titled “Statistical Static Timing Analysis using a Skew-Normal Canonical Delay Model". PUBLICATIONS

“Statistical Static Timing Analysis using a Skew-Normal Canonical Delay Model,” Design, Automation and Test in Europe Conference and Exhibition (DATE), DOI: 10.7873/DATE .2014. 271, 2014 IEEE.

EXTRA CURRICULAR

Hobbies as trekking, cycling and playing Table Tennis & cricket.

Has Green belt in Korean martial arts called Hapkido.

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