RAJIV KUMAR CHOUDHARY

**th main, BTM Layout stage 2

Bangalore - 560076

acq6f1@r.postjobfree.com

Mobile: 886-***-****

Objective: To learn as well as contribute at every opportunity as ASIC verification engineer with good learning (in especially system Verilog/UVM/assertions), while participating in an energetic, team-oriented, success-seeking atmosphere.

Currently Employed: Wipro Technologies, Bangalore (from July ’11)

Previous employer: iWave Systems Technology, Bangalore (from Dec’2009-June ’11)

Qualification:

Bachelor of technology (Electronics and Communication Engineering),passed in year 2009 from Manipal Institute of Technology, Sikkim

Certificate in VLSI verification (using cadence tools) from August 2009-Dec2009,from Accel IT Academy, Bangalore (systemverilog, assertions and coverage)

Work Experience:

5.6 years’ work experience in ASIC frontend verification

Ability to initiate and accomplish numerous tasks

Very ambitious, highly responsible and hardworking

Technical Skills :

Operating System: WindowsXP,Ubuntu,VNC server on Linux using vim/gvim editor

HDL-HVL Languages : Verilog, basic VHDL, SystemVerilog, UVM,OVM

Domain: ASIC/FPGA Design Flow, Digital Design and verification methodologies

Knowledge: RTL coding, FSM based design, Testbench Coding, Simulation, Code Coverage, Functional Coverage

Protocols knowledge: GPIO, RAM, EDRAM, basic OCP,SPI,SFDP, basic i2c, EMIF16, Basic AXI, AHB

EDA Tool: Incisive Enterprise Simulator NC-Verilog, QuestaSim, Modelsim, Verdi and ISE, VCS, Xilinx ISE,DVE

Projects undertaken:@WIPRO

Project: INTEL_CSG_SPI_VER_VS (Duration:June’15-current;Team Size:07)

Description: The SPI/espi has different controllers like CSME controller, BOOT controller,IE controller,TPM controller performs the access control operation over the flash through the security checks,SAI values.The IOSF primary and IOSF sideband interface is connected to the controller,through bfm,which has control for the device master select,and configures the master to access the flash through the security engine,attached to the spi/espi interface.

Task Description:

*To ramp up the JEDEC SFDP,eSPI/SPI protocol and controller specification

*To study and understand OVM environment and understand the Intel’s SAOLA environment flow

*To run regression and verify the result & debugging with team

Project: ALU Env Verification (Duration: Mar’15-May’15; Team Size: 01): Internal

Description: The ALU performs simple operation of addition, subtraction, multiplication, division, xor, and, buffer operation. The simple ALU operation is being tested by building UVM environment as a learning assessment.

Task Description:

*Coding the SV-UVM environment for ALU

*Understand the UVM working ways and make the environment in run-phase.

*Running of sanity test case with a random sequence,

*Debugging and correcting the compilation and runtime errors in simulation

Project: NEC LTE BTS HW MAIN (Duration: Aug’14-Feb’15;Team Size:02)

Description: The project is based on the RF data transmission and reception at the base station, via CIPRI protocol where the base station is being controlled by CPU Interface FPGA. The CPU IF has the GPIOs, UART selection if, SPI master interface, EMIF16 slave interface, power and reset sequencing interface, LED interface. The CPU IF is the basic controlling block which provides the power and reset to other chips on the board based on its configuration of its local registers.

Task Description:

*Documentation of the testplan and verification environment

*Reading through the specification for the CPU IF block level FPGA interfaces and documentation of the verification plan for CPU IF

*Coding & debugging of the verification environment with testcases for the CPU IF BFM using systemverilog and integration of the RTL with testbench top.

*Regression test run through script file

Project: Dopplerd Wrapper Memory Verification (Duration:Jan’13–June’14;Team Size:06)

Description: This project is about the core memory wrapper verification, where the designers have the vendor and wrapper memory implemented. The RAMWRAP_1RW, RAMWRAP_1R1W, EDRAMWRAP_1RW, RAMWRAP_1RW, EDRAMWRAP_2RW having different ports for write and read access were used. This project is about the core memory wrapper verification. The designers have vendor memory and it wrapper implemented.

Task Description: Wrapper verification (EDRAM, RAMWRAP)

*Written perl script to extract parameters from the given caplist file.

*Converted the Verilog BFM logic into system Verilog driver, generator, and interface; integrated DUTs in testbench top module.

*Run basic test and check the compilation issues, and bring up to run phase

*Run memory testcases, regression tests and debug failures using makefiles for configuration and switch selection, and parameter argument passing

*Using makefiles for configuration and switch selection, and parameter argument passing

Project: DopplerCS GLS verification (Duration:July’13 – Dec’13;Team Size:06)

Description: This project is at the stage of gate level netlist debug phase. The basic part concept of design is that the packet flows via CPU interface, PCI express root complex through the fifos, and network interface. The environment is done in system Verilog based VMM methodology, for GLS.

Task Description:

*Verification of the testcase scenario and review the scenario and debug the ‘X’ propagation and test failures

*Simulate and debug the testcase and waveform viewing

*Debugging the “X” propagation and logic failure of testcase, trace the failing module

*Using makefiles for configuration and switch selection, and parameter argument passing

Project: Lattice POJO2 verification (Duration:Nov’12 – June’13;Team Size:06)

Description: This project is a part of the Lattice’s ASC (application specific circuit) verification project. This project has one ASC model which mainly analog behavior mimic and XO2 DUT. There are 10 DUTs connected to the ASC model via Three wire interface. This provides the different temperature; voltage to the Xo2 via ASC’s which controls the values based on the threshold check. The environment is done in system Verilog based UVM methodology.

Task Description:

*writing testcase based on the item list for the given scenario

*Simulate and debug the testcase and waveform viewing

*Writing sanity test sequences code for the UVM environment and debugging it

*Debug regression failure

*guide junior team member and help understand the UVM environment

Project: Macro Verification (Duration: May’12 – Oct’12; Team Size:11)

Description: This project is mainly about the PWM generation, ADC macro. This has two modules, BRGA macro and GENA macro. The BRGA macro has an APB interface, installation of 4 sets of 11 bit timer counter and 11 bit compare register. It outputs 4 enable signals for operating PCLK intermittently; baud rate generator. It possesses the function that performs emulation by SVSTOP input. The BRGA register configuration determines the baud rate generation cycle. The GENA macro used the 4 outputs of the BRGA macro. It has APB interface,12bit timer counter and, two 12bit compare register,13bit compare register installation .It possesses timer output PWM& an interruption signal, an AD trigger output and 4 input clock enable BRGA. It has input terminal for Support for simultaneous start by PIC connection. The register configuration of GENA determines the duration when interrupt is generated and hence the duty cycle is configured for the PWM signal

Task Description: Verification of the testcase scenario and review the scenario

*writing testcase based on the item list for the given scenario in SV environment.

*Review the testcases written by testcase owners

*Simulate and debug the testcase and check the correctness with the item list and waveform viewing

Project: Iosf2ocp bridge verification (Duration:Aug’11 – Mar’12;Team Size:03)

Description: The bridge consists of two protocols IOSF (Intel On-chip System Fabric) and OCP (open core protocol).The bridge maps the interface of the two specifications so that any data transfer can be easily done from IOSF through the bridge to other devices connected through OCP and vice versa.

Task Description: verification of the Iosf2ocp bridge

*To ramp up the OCP protocol and bridge specification

*To study and understand OVM environment and understand the environment flow

*To check coverage report for the bridge and add coverage code for the clock gating and out of bound interrupts, as required scenario for its functionality based on the specification given

*To do white box coverage checking using system verilog assertions

*To run regression and verify the result & debugging with team

Projects undertaken:@iWave Systems Technology

Project: RADAR capture card FPGA (Duration:Apr’11 – June’11;Team Size:04)

Description: The RADAR capture card is used to capture the Radar return data and store it in the digital form into DDR2 RAM memory which acts as initiator to initiate the transmission of data from the PCIE end point to the root port. The root port initially configures the target then waits for the response. The packet contains the different azimuth value, azimuth count and time and the data with respect the sync signal captured. The design has i2c interface which is used as programmable clock and SPI interface and PCI express interface.

Task Description: Verification of the RTL of Radar capture card FPGA

*Written & documented different test plan and test cases for the test bench covering the functionality of the Radar Capture card FPGA

*Written the test bench code for the verification, integrating the PCI express BFM provided by Lattice semiconductor at transaction layer level, and DDR2 BFM provided by Micron

*Using Simulation Environment in Verilog HDL to verify.

Project: AIS DH receiver system (Duration: November’10 – Mar’11; Team Size: 04)

Description: The AIS DH system is used in the satellites for receiving the demodulated data. The demodulated data is then stored through the FPGA into the NAND flash memory for different channels. The receiver system receives the data from outer environment using different communication methods such as UART, Two-wire interface, synchronous serial communication. The data processing is done based on the OBC (on board computer) commands which controls the system.

Task Description: Verification of the RTL of AIS DH receiver system

*Written & documented different test plan and test cases for the test bench covering the functionality of the AIS DH receiver system

*Written the test bench code for the verification & integrated the available NAND flash BFM from Micron into the simulation environment.

*Verified the design using Simulation Environment in VHDL HDL.

Project: V53A Microprocessor (Duration: December’09 – Oct’10; Team Size: 10)

Description: Porting of 16-bit V53A microprocessor for Xilinx Spartan 6 FPGA. It is similar to the working of 8086 microprocessors with new added features for DMA, Timer, Interrupt and SCU unit. This is a prototype for the client’s ASIC processor used in the PLC which is replaced by V53A microprocessor on Spartan 6 Xilinx FPGA

Task Description: Verification of the RTL of 16-bit V53A microprocessor

*Written & documented different test plan and test cases for the test bench covering the functionality of the core processor and the peripherals.

*Written assembly code for the processor verification

*Verified exhaustively with 1000 cases, using directed testing method

*Verified the available design using Simulation Environment in Verilog HDL.

*Target testing support with team, using PLC FPWIN software tool, hypertext terminal and Xilinx chip-scope pro

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