Engineer Test Cases

Ali Ziaie

**** ******* *** *.

Richfield, MN ****3

Cell: 512-***-****

Email: acq6cw@r.postjobfree.com

OBJECTIVE:

Looking for a challenging role in a dynamic organization where my skills and interest in the field of Java programming or web development help in business/user information solutions.

PROFILE:

Diverse experience in software, hardware and management

Certified Java Programmer

Seven years experience in management position. Major strengths include strong leadership, competent, attention to detail, as well as supervisory skills including hiring, termination, scheduling, training, payroll, and other administrative tasks

Ten years software experience in VHDL and Perl programming

Ten years experience in design verification of models consisting of CPU and IO chips

Training/Educational Classes/Certification:

JavaScript 05/2015-08/2015

HTML5, CSS3 02/2015-04/2015

Java Certification Associate (1Z0-803 Java SE 7 programmer) 12/22/2014

Java 10/2014-12/2014

Python 08/2014-09/2014

Verilog HDL . 07/2014-08/2014

TECHNICAL SKILL SET:

Languages: Java, HTML5, CSS3, JavaScript, Python, VHDL, Verilog, C, C++ and Perl

Hardware/OS: Linux, RS6000/UNIX (AIX), IBM/MS-Windows, and Macintosh

Software: Eclipse, Excel and Microsoft Word

EXPERIENCE:

Apadana LLC, Minneapolis, MN

Consultant 01/2015- Present

Provide technical support for hardware, software and company web site

Provide management support in the areas of reducing operational cost, employee payroll, hiring, scheduling, productivity conduct and evaluation

Provide guidance and policy for working with private and government agencies

Provide guidance and policy for auditing process and business proposal to customers

Provide progress report and company financial forecast to the management

Extreme Fun, Inc., Austin, TX

Manager 06/2007- 07/2014

Execute strategic planning, business development and securing funds

Increasing profit by emphasizing on customer satisfaction and reducing operational cost

Supervising the external affairs of the company with private and government agencies

Making financial decisions, managing the budget and organizing the fiscal documents

Supervising & evaluating performance & productivity, recruiting & training new employees

Implementing policy and procedures for the company to maximize employees productivity

IBM, System Verification Group, Austin, TX

System Design Verification Engineer 06/2000-11/2006

Responsible for Asic chip Galaxy2 verification process with POWER 6 at system level.

Provided direction, guidance and resources to other engineers

Modify verification process and positively affect final product quality and delivery.

Simulation-based verification of RTL design with special emphasis on IO interface.

Discovered bugs, characterized them, offer appropriated solutions, and regressed bugs.

Reviewed project specifications; generated test plans, test cases, and testing libraries.

Reported appropriate bug-tracking statistics and estimated finish dates to technical team.

VHDL coding, setting system environment, model configuration/build/bring up and simulation of IBM’s Hubs and Bridges, such as: Enterprise, Winnipeg, P5IOC, P5IOC2, Galaxy, Galaxy2, Calgary, Calioc2 and CalgaryE in system models.

Verification of pSeries Squadron's P4 (Regatta) and (P5) PowerPC multi-processor chip, Nway and all IO System simulation at chip and system level.

Automated the build process and models promotion using Perl script for system models.

Delivered all commitments to our customers, on time and with high quality.

Creating test cases for static/random regressions on chip/system models, tracker triage and release chip/system models to the verification design community.

Scandef generation for IBM’s Asic chips Canopus Plus and Calgary (IBM’s bridge chip).

IBM, Rochester, MN

Tools Support / Verification Engineer 06/1996-06/2000

Provided tool support and problem resolution for Rochester and selected off-site users in the areas of VHDL language usage, compilers and Logic simulation.

Worked with EDA/vendor developers to ensure that VHDL and logic compiler/simulation tools meet customer requirements and are delivered in a timely manner.

Developed new tools and integrates code in the above areas as necessary to supplement EDA/vendor offerings.

Created HTML documents; ensuring customers understand how to use EDA tools and methodologies in their workflow.

Developed Perl scripts for compilers (TexVHDL, MTI vcom) and simulator (MTI vsim) in Lpad for Rochester and Austin site.

Writing VHDL codes for IBM Packages. Providing reusable codes for logic programmers.

Ensured that new tools and rules (IBM VHDL Libraries/Packages) are adequately tested before they are put into production.

EDUCATION:

Master of Science, Electrical Engineering, University of Minnesota, Minneapolis, MN

University of Minnesota, Minneapolis, MN, Finished all courses for Master of Science in Mathematics

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