Design Engineer
Resume:
MOSIN ABDUL
Email : ******.*******@*****.***
Mobile : +91-950*******
PLANNED OBJECTIVE:
To pursue career in VLSI industry, in a progressive organization that gives scope to enhance my knowledge and to ensure my highest level of contribution towards the organization I work for, with dedication and hard work. DOMAIN SKILLS:
ASIC Design:
Tools : RTL compiler, SoC Encounter, NC Verilog, Xilinx ISE 13.1 Topics : Synthesis, STA, Floor-plan, Power-Plan, PnR, CTS, Routing, Physical Verification.
Full-Custom Design:
Tools : Cadence Virtuoso, Cadence Assura
Topics : CMOS, LVS, DRC, RC Extraction.
Hands-on experience on 180, 90 and 45 nm Technologies
Programming Languages : C, Verilog
Scripting Language: TCL, PERL (Beginner)
Command on Logic Design concepts, FSM and CMOS Circuit Design
Good Understanding in ASIC and Full Custom based design flows PROJECTS :
During training at CVCP :
Design of DTMF Chip from Net-list to GDSII
Responsibilities : Floor Planning, Place & Route, Clock Tree Synthesis and Physical verification of DTMF Chip using TSMC 45nm Technology.
Tools Used : SoC Encounter
Cell Count : 5 K
Macro Count : 6
Challenges faced : Deciding the orientation and location of Macros during Floor plan. Eliminating setup and Hold violations.
Layout Design and verification (DRC, LVS, RCX) of CMOS Inverter and Basic Gates using Cadence Virtuoso in 180nm technology.
Mini project on Up-Down Counter.
Academic Projects During M.Tech :
Low Latency Galios Field Polynomial Multiplier over GF (2 m
)
Description: Finite field GF(2m) arithmetic is becoming increasingly important for a variety of different applications including cryptography, coding theory and computer algebra.
Responsibilities: Design and verification of Galois Field Polynomial Basis Multiplier, synthesizing of blocks using TSMC 135nm, 65nm and 40nm technology files and Reports generation.
JTAG Interface on SOC :
Description In today’s complex systems, testability is an increasing concern in almost every application and in every area of application development. Manufactures that thoroughly address the issue of testability at the device, board and system levels deliver more consistently reliable and cost effective products to the market.
Team Size : 3
Tools Used : RTL Compiler
Responsibilities: Synthesizing of Blocks, Power and Area calculations of Top Module and Reports generation.
Academic Projects During B.Tech :
Project titled “Digit Analysis in CS-CORE”.
Mini project on “DTMF Based Voting Machine”.
CERTIFICATIONS AND PUBLICATIONS:
Completed training as a trainee engineer in Cadence VLSI Certification Program
(CVCP) conducted by the Cadence Design Pvt Ltd, Bangalore, for a duration of six months in ASIC Flow from RTL to GDSII.
Published paper on “A Novel Polynomial Basis Multiplier for Arbitrary Elliptic Curves over GF(2
m
)", In IEEE's international conferences for convergence of technology, 6th April – 8th April 2014, Pune, India.
Attended “Autonomous Microcontroller Robotics” workshop in 2010, conducted in JBIET, Hyderabad.
Presented paper titled :
“Digital light processing” at Osmania University on the event of Mecharena in 2010, Hyderabad.
KEY STATEMENTS ABOUT MYSELF:
A quick learner with good communication skills and enthusiastic in learning new things.
Approachable to any critical circumstances in a positive manner. ACADEMIC QUALIFICATION:
Qualification
(Stream/Branch)
College
(Board/University)
Period of
Study
Percentage of
marks secured
PG Diploma in
VLSI
Cadence VLSI Certification
Program(CVCP), Hyderabad
2013 -
M.Tech (DECS) Vardhaman College Of Engg.
(Autonomous),Hyderabad
2011-14
68
B. Tech (ECE) JB Institute of Engineering and
Technology, Hyderabad
2007-11 65.36
Intermediate
(M.P.C)
Board of Intermediate
Education, A.P.
2005-07
94.5
S.S.C
Board of Secondary
Education, A.P.
2004-05
87.33
PERSONAL DETAILS:
Father’s Name : Abdul Ghani
Date of Birth : 20th August, 1990
Passport Number : L6016094
Languages Known : English, Telugu, Hindi and Urdu
Hobbies : Listening to Music and Travelling
Place:
Date:
(Mosin Abdul)
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