Vlsi Design, Asic, Fpga, Verilog, Vhdl, Dft, Atpg, Digital Design

Sarang. S. Samangadkar

M.Tech, VLSI Design

Mobile:- +91-909******* / 982-***-****

E-mail: ******.******@*****.***

Looking for a challenging career to achieve a dynamic role in VLSI Design that will offer be the best opportunity for further development of my abilities, skills and knowledge in an established firm with long term career growth possibilities.

Master of Technology (M.Tech) in VLSI Design with distinction having CGPA 8.53, from VelTech University, Chennai.

Bachelor of Engineering (B.E.) in Electronics and Telecommunication with Ist Class having 60%, from Shivaji University, Kolhapur.

M.Tech Project

Title : Fault Diagnosis in Ternary Logic Circuits

Description : This project diagnoses the logical faults present in Ternary combinational Logic Circuits by generating the no. of test patterns. We used the Tanner tool for generating Schematics, Netlist, & their Waveforms. Further we used C language platform for test generation. M.Tech Minor Project

Title: Traffic Light Controller using VHDL

Description : This project is designed with the help of VHDL language platform on Spartan-3 FPGA based Traffic Controller kit. The softwares used for programming is Xilnx ISE v8.1. For simulation we used Altera’s ModelSim simulator. The duration for this mini project was one month. B.E Graduation Project

Title : Design of a Touch Screen Mobile Phone

Description :

In this Project, we designed the Touch Screen based mobile phone with user friendly accessing and innovative features. We used the raw GSM modem for communication purpose, the Graphical LCD is used for displaying CALL & SMS information, the touch-screen keypad is used for user interface purpose. The buzzer & the receiver is used to ring and receive the calls resp. For all these scenario control, we used AVR ATMega32 microcontroller. The programming platform we used is Embedded C Programming. Graduation minor project

Title : Sinusoidal PWM Generator

Description :

It is a project in which Sinusoidal Pulse Width Modulation (PWM) using Op-amp 741 is implemented & which is operated on 5v Power Supply. We designed & combined four circuits i.e. Wein Career Objective :-

Educational Qualification:-

Project Details :-

Bridge Oscillator to generate sine wave, Triangular Wave Generator to generate Triangular Wave, Inverting Amplifier, and lastly the Comparator.

RTL Coding by VHDL & VERILOG, CMOS VLSI Design, FPGA, Physical Design, IC Fabrication, ASIC Design & Verification, UVM/OVM Methodology, Design For Testability (DFT), Automatic Test Pattern Generation (ATPG).

Software :- Xilinx ISE v8.1/9.2/14.7, Cadence Virtuoso & Encounter, Matlab, Tanner tools.

Hardware :- FPGA Spartan 3E

Languages :- VHDL, VERILOG, ALP in microcontrollers, C Programming

Hobby Projects :- Traffic Light controller using VHDL, Electronic Piano using 555 timer

Presented paper on “4G Technology” at National TECH-SYMPOSIUM 2k11 held by DKTE Institute, Ichalkaranji.

Attended workshop on “Cadence EDA” at Vel-Tech University, Chennai.

A paper on “Fault diagnosis in Combinational Logic Circuits : A Survey”, published in International Journal on Scientific and Research Development (IJSRD).

Attended Workshop on “Emerging Trends in Embedded Systems” at Chennai.

5 Exams of Classical Singing passed.

State Level & University level prize winner for Singing Competition

3 year winner in “Traditional Day” in Socials

Leadership in cultural programs in college

Date of Birth :- 26th December, 1989.

Marital Status :- Single

Strengths :- Focussed, Event manager, Group leading ability, Patient Languages :- English, Hindi and Marathi

I hereby declare that the particulars furnished above are true to the best of my knowledge and belief.

(Sarang S. Samangadkar)

Area Of Interest

Technical Skills

Training/workshops :-

Publications :-

Extra Co-Curriculars:-

Personal Details:-

Contact this candidate