Design Manager

**-*, ***** **.-**, Munnireddy

ABHINASH MANDAL Layout, Panathur,

E-mail: **************@*****.*** Bengaluru-560103

Mobile No.: +91-991*******

SUMMARY:

M.Tech in Microelectronics and VLSI Design (2013-2015) from NIT Calicut with 7.55

CGPA.

Good understanding of complete ASIC design flow.

Good knowledge on Digital design, Static Timing Analysis (STA) and Low Power

Design.

Good communication skills and having ability to work as part of a team.

CARRER OBJECTIVE:

Seeking a challenging career in VLSI, where I can utilize and enhance my technical as well as

interpersonal skills while providing valuable contribution to the organization.

TECHNICAL SKILL AND TOOLS:

HDL VHDL

Scripting Language Perl

Programming Language C and MATLAB

EDA Tools Cadence-Virtuoso, SoC Encounter, Xilinx ISE

SPICE Simulator LTspice

Hardware Xilinx Spartan-3E FPGA

Verification Methodlogy UVM (Theoritical Concept)

Communication Protocol UART

AREA OF INTERESTS:

ASIC Design

M.TECH MAJOR PROJECT:

Title: Analytical modeling of Graphene Nanoribbon Field Effect Transistor (GNRFET).

Aim: 1.To obtain an analytical model for the I-V characteristics of GNRFET based on semi-

classical ballistic transport.

2. Implement the model as library to design high speed digital circuit.

Description: Graphene is a 2-dimensional material with a hexagonal molecular structure. It has

remarkable properties which include high carrier mobility, which results high switching speed to

GNRFET compare to silicon MOSFET.

Challenges: 1.To model the transistor based on semi-classical ballistic transport.

2. Implement the model as a library in Cadence-Virtuoso.

3. To design an inverter circuit based on that library.

Tool: MATLAB, Cadence-Virtuoso

HDL: Verilog-A

COURSE PROJECT:

FPGA Implementation of DES Encryption and Decryption using RS232 Interface in VHDL and

implemented on Spartan-3E FPGA kit.

Tool: Xilinx ISE.

Design of multi VT CMOS logic circuit to reduce leakage power using sleep transistor.

Tool: LT-SPICE.

EDUCATIONAL QUALIFICATION:

M.Tech in Microelectronics and VLSI design (2013-2015) at National Institute of Technology

Calicut (Kerala) with 7.55 CGPA.

Completed B.Tech in Electronics and Communications Engineering (2008-2012) from

College of Engineering and Management, Kolaghat affiliated to WBUT Kolkata with 7.68

CGPA.

CO-CURRICULAR AND EXTRACURRICULAR ACTIVITIES:

Presented a seminar on Strained Si Technology at National Institute of Technology, Calicut.

Secured 3rd position in Robotics (Resonsnce10 Organized by CEM, Kolaghat).

Achieved National Cadet Corps (NCC) C certificate and NCC B certificate.

Vocational Training at BSNL Kalyani (NSCBTTC) based on-Fundamentals of Communication

System.

PERSONAL DETAILS:

Gender Male

15th Sep 1990

Date of birth

Language Known Hindi, English, Bengali

DECLARATION:

I hereby declare that the above mentioned details are true to the best of my knowledge.

Date: 05/08/2015 ABHINASH MANDAL

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