EDUCATION:
M.TECH -VLSI & EMBEDDED SYSTEMS
B.TECH-Electronics & Communication Engineering
College of Engineering, Kottarakkara
JERIN JAMES
M.TECH -VLSI & EMBEDDED SYSTEMS
PERMANENT ADDRESS PRESENT ADDRESS
Kaniyamparampil House, 18, Rachana Society,
Bethany Church Road, Near Kalupur Corporative Bank,
Thiruvalla. Shivranjani Cross Road,
Pathanamthitta (Dist). Satellite Road,
Pin:689101 Ahmedabad – 380015,
Kerala. INDIA.
INDIA.
: **********@*****.***
: +919********* (M)
Objective
Seeking a career enriching responsible job with an opportunity for professional challenges to use my knowledge in the best possible way for achieving the company’s goals and enhance my professional skills.
Summary
Electronics Engineer with M.Tech in VLSI and Embedded Systems with a CGPA of 8.29 in 2013-2015.
B.Tech in Electronics and Communication Engineering with an aggregate of 79.36% in 2009-2013.
Good knowledge in C, VHDL and Verilog.
Expert in Cadence EDA tools for Analog and Digital Design.
Hands on experience on TMS320C54X DSP Kit, Spartan 3 and Spartan 3E FPGA kit.
Strong analytical and problem solving ability.
One year experience as Intern in ISRO, Thiruvananthapuram during the academic year 2014- 2015.
Educational Qualifications:
COURSE
INSTITUTION-UNIVERSITY
YEAR
AGGREGATE
M.TECH ( VLSI and Embedded Systems )
Toc H Institute Of Science and Technology,
Cochin, Kerala.
(Cochin University of Science & Technology)
2013-2015
8.29
(CGPA)
B.TECH (Electronics & Communication Engineering)
College of Engineering, Kottarakkara, Kerala.
(Cochin University of Science & Technology)
2009-2013
79.36%
Class 12
St. John’s Higher Secondary School,
Mavelikara, Kerala. (Kerala State Education Board)
2009
88.23%
Class 10
B B G H S, Nangiarkulangara, Kerala.
(Kerala State Education Board)
2007
94.00%
PROJECT:
Asynchronous ALU
DEAF AID TELEPHONE SYSTEM
AUTOMATIC SENSOR BRIDGE
EXTRAS:
National Service Scheme member
Academic Projects & Seminar
DESIGN OF AN ASYNCHRONOUS ALU @ ISRO, Thiruvananthapuram, Kerala.
Description:
M.Tech Project
Developing an Asynchronous Digital Design Methodology and Design of an Asynchronous ALU
Platform : Synopsys, Cadence
Duration : 1 year
Group Size : 1
BIO-INSPIRED HARDWARE (Seminar)
Method of creating systems that mimics real world
DEAF AID TELEPHONE SYSTEM
Description:
B.Tech Major Project
Convert the words from a normal person into text for a deaf person and vice versa with a data base.
Platform : PIC
Duration : 5 months
Group Size : 5
DIGITAL STEGANOGRAPHY (Seminar)
Technique for hiding Secret Messages.
AUTOMATIC SENSOR BRIDGE INTEGRATED WITH PROTECTION SYSTEM (Mini Project)
Description:
B.Tech Mini Project
Automatic folding of bridges when a ship passes through, integrated with an automatic weighing system to detect overloaded vehicles.
Platform : PIC
Duration : 4 months
Group Size : 4
Extra Curricular Activities
Organized and volunteered various programs by IEEE.
Attended various programs and camps organized by the N.S.S Unit of the college.
Participated in various dance programs in college.
Achievements
Robotics competition conducted by Technophilia zonal level: Came under
Top five groups.
TECHNICAL:
Technical Skills
Languages
C, VHDL, Verilog
EDA tools
Cadence EDA tools for Analog and Digital Design
Operating System
Windows, Linux
Subjects of Interest
VLSI, Digital Electronics
Others Tools
Xilinx ISE, Proteus
Hands-on experience on TMS320C54X DSP Kit, Spartan 3 and Spartan 3E FPGA kit.
References
#
Name
Designation
Organization
1
Dominic George
Joseph
Scientist
Vikram Sarabhai Space Centre, ISRO, Thiruvananthapuram, Kerala.
Email: *******@****.***.**
2
Sudheesh Madhavan
Associate Professor
Department of Electronics and Communication, Toc H Institute of Science and Technology, Aarakkunnam, Cochin, Kerala.
Email: *********@**********.***.**
PERSONAL DETAILS
Name:JERIN JAMES
Passport No: J0458892 (Date of Expiry: 10-10-2020)
Mother Tongue: MALAYALAM
Date of Birth: 12- 12-1991
Sex: FEMALE
Marital Status: MARRIED
Nationality: INDIAN
Languages known: Malayalam, English, Hindi
Hobbies:Reading Books, Listening Music
Areas of Interest:VLSI, Digital Electronics
PAPER PUBLICATION
Paper Title:Asynchronous Designs
Paper ID:IJECE-V215P102
Published inVolume 2 Issue 5 – May 2015 issue
Paper Link:www.internationaljournalssrg.org/IJECE/2015/Volume2-Issue5/IJECE-V2I5P102.pdf
DECLARATION:
I hereby declare that the information furnished above is true to the best of my knowledge.
JERIN JAMES