Microsoft Office Engineer
Resume:
PRIYANKA ATTIGUPPE ASHOK
************@*****.***
www.linkedin.com/in/ashokpriyanka
CORE COMPETENCIES:
Talented in ability to apply and integrate knowledge.
Versatile in logical and critical thinking; and creative problem solving abilities.
Possess interpersonal, communication, leadership skills, especially collaborating on teams.
capable professional with strong work ethics.
EDUCATION:
Illinois Institute of Technology, Chicago, IL Expected: December 2015 Master of VLSI and Microelectronics
Vidya Vardhaka College of Engineering, Karnataka, India Bachelor of Engineering in Electronics and Communication June 2012 COURSEWORK:
Advanced Computer Architecture
Advanced VLSI Systems Design
VLSI Architectures for Signal Processing and Communications EXPERIENCE:
Kaynes Technology India Pvt. Ltd.( Intern) April 2013- August 2013
- Assembled components onto the printed circuit boards (PCB).
- Checked the quality of the printed circuit boards (PCB). ACADEMIC PROJECTS :
FinFET Transistor Characterization and Implementation of AOI21 Gate in Different Modes Spring 2015
- Investigated nMOS and pMOS FinFET for dc transfer characteristics
- Analyzed the delay and power of an inverter in short gate and low power mode
- Compared the delay and power of an AOI21 gate in short gate, low power, hybrid and independent gate mode using HPICE.
Simulation of Cache, CPU, Memory and Data Path Spring 2015
- Studied the working of cache and memory.
- Coded in VHDL for the architecture.
- Verified the working of the architecture using a test bench.
Discrete Cosine Transform (DCT) Implementation Based on Algorithmic Strength Reduction and BinDCT Algorithm. Spring 2014
- Generated the DCT function in 2 types of architectures.
- Compared them in terms of area, time and power consumed.
Design and Simulation of a MIPS CPU Summer 2013
- Designed a custom RISC processor.
- Executed the data path and the control unit.
Design and Synthesis of Multi-Operand Adders. Fall 2012
- Implemented a multi-operand adder in ASIC flow for designing a digital circuit.
- Consisted of redundant digit adders such as [3:2], [5:2] carry save adders.
ASIC Implementation of Watermarking Encoder February 2012 - June 2012
- Coded in Verilog for visible and invisible watermarking using CADENCE tool.
- Established test benchmarks for the code to obtain simulations.
- Synthesized the simulated code using CADENCE Encounter tool.
Single Cycle Processor with Data Path only November 2011
- Coded processor which can execute a defined instruction set in Verilog.
- Tested the code for its functionality.
PRIYANKA ATTIGUPPE ASHOK
************@*****.***
www.linkedin.com/in/ashokpriyanka
TECHNICAL SKILLS:
EDA Tools : Cadence Virtuoso II, Xilinx ISE, Modelsim
Languages : C, VHDL, Verilog, 8051 Assembly, 8086 Assembly
Operating systems : Linux, Windows.
Microsoft Office Suite : Excel, Word, PowerPoint TECHNICAL PAPERS:
"Design of a reversible barrel shifter," VVCE, Karnataka, India. April 2012
"Surface Plasmon in metal nanoparticles and applications, "IIT, Chicago, Illinois. Fall 2014
"Optical fiber sensors, " IIT, Chicago, Illinois. Spring 2015 ACHIEVEMENTS:
Elected as the Class Representative for the academic years 2010-2011, 2011-2012
IEEE member for the academic years 2010, 2011 and 2012
Participated in a two day National conference on “Entrepreneurial Opportunities in Home Grown Businesses for Women”, 2010
Represented VTU in South West Zonal Tennis Tournament at the university level in the year 2011.
Successfully trekked one of the peaks of the Himalayas in the year 2014.
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