uvm sv

Sindhu Senguttuvan

No.***, Flat A*, Anuda homes, Balaiah Garden, Madipakkam, Chennai-600091

Phone: 996-***-**** ********@*****.***

experience SUMMARY

* ***** *** * ****** of experience in verification of FPGA\ASIC.

Extensive experience in verilog, System Verilog and UVM.

Extensive experience in developing test plan and test bench architecture.

Extensive experience in developing System Verilog and UVM compliant test

bench.

Extensive experience in developing Verification IP’s.

Extensive experience in writing constraint random test cases using system

verilog.

Extensive experience in writing system verilog assertions and functional

coverage.

Extensive experience in developing coverage analysis reports using VMM

planner.

Experience in using version control tools like SVN and GIT.

Experience in using tools like VCS, MTI.

Experience in writing Perl scripts.

Extensive experience in using tools like Bugzilla and TRAC for bug tracking .

Hands on experience in using Zebu emulation tool.

Has ability to adopt to new technologies, a good team player and has good

communication, planning and organizing skills.

Professional EXperiencE

HCL Technologies : October 2012 – Till date

Qualification

Bachelor of Engineering in Electronics and Communication Engineering, GCT

Coimbatore, 2012, 8.4/10.

TamilNadu Higher Secondary Examination, Sri Vijay Vidhyalaya GHSS,

Dharmapuri, 95%

TamilNadu Matriculation Examination, Sri Vijay Vidhyalaya GHSS, Dharmapuri, 89%

Awards & REcognition

• Live Wire Award during quarter OND 2014 for excellent contribution to aurora VIP

development project.

• Rated as an exceptional performer for Jul’13-Jun’14 project performance.

Project Details

1. CAN UVC design and verification

Designed and verified a VIP compliant to CAN protocol .The VIP consist of a FIFO TX/RX

agent, register agent and CAN UVC.

My Role in the Project / Key Assignments:

• Prepared feature list, test plan, test cases and verification architecture document.

• Developed the test bench environment.

• Developed scripts using perl.

• Designed and verified the FIFO TX and RX agent,CAN agent(SV, UVM).

• Identified functional coverage features.

• Performed register model integration.

• Participated in architecture and design reviews.

2. XILINX VIP design and verification

Designed and verified a VIP compliant to Aurora 8b/10b protocol. The verification

component for verifying Aurora 8b/10b protocol is system verilog and UVM compliant. The

environment consists of a transmitter agent and receiver agent.

My Role in the Project / Key Assignments:

• Prepared feature list, test plan, test case and verification architecture document.

• Participated in architecture and design reviews.

• Developed the test bench environment.

• Developed scripts using Perl.

• Designed and verified the receiver agent (SV, UVM).

• Identified functional coverage points and did coverage coding.

• Prepared coverage analysis report using VMM planner.

3. XILINX VIP design and verification

Designed and verified a VIP compliant to Aurora 64b/66b protocol. The verification

component for verifying Aurora 64b/66b protocol is system verilog and UVM compliant.

The environment consist of a transmitter agent and receiver agent.

My Role in the Project / Key Assignments:

• Prepared feature list, test plan, test case and verification architecture document.

• Participated in architecture and design reviews.

• Designed and verified the receiver agent (SV, UVM).

• Identified functional coverage points and did coverage coding.

• Prepared coverage analysis report using VMM planner.

4. MIPI CSI2 Transmitter Design and Verification

Verified the MIPI CSI-2 protocol compliant CSI2 transmitter design.CSI2 Transmitter

verification environment has the PPI interface to receive the data from the D-PHY and the

Pixel interface to transmit the pixel data. It supports APB interface for register access.

My Role in the Project / Key Assignments:

• Prepared test plan and test cases for verification.

• Designed and verified the register agent (SV, UVM)

• Verified the CSI2 Transmitter design.

• Integrated the register model.

• Prepared coverage analysis report using VMM planner.

• Ran regressions to meet hundred percent coverage.

5. MIPI CSI2 Receiver Design and verification

Verified the MIPI CSI-2 protocol compliant CSI2 receiver design.CSI2 receiver verification

environment has the PPI interface to transmit the data to the D-PHY and the Pixel

interface to packetize the received pixel data. It supports APB interface for register

access.

My Role in the Project / Key Assignments:

• Prepared feature list, test plan and test cases for verification.

• Participated in architecture and design reviews.

• Designed and verified the pixel agent (SV, UVM)

• Designed and verified the register agent (SV, UVM)

• Integrated the register model.

• Identified functional coverage points and did coverage coding

• Wrote system verilog assertions on the pixel interface.

• Prepared coverage analysis report using VMM planner.

• Ran regressions to meet hundred percent coverage.

6. Waddell Creek Asic Verification

Design and verification of Waddell Creek (WCK) wireless chipset. WCK provides PCIe

(Gen 3) interface for connectivity to the processor subsystem, with Common Public Radio

Interface (CPRI).CPRI cluster module consist of 6 CIPRI links with 8 antenna carriers

each. Part of cluster verification team.

My Role in the Project / Key Assignments:

• Verified the CIPRI TX/RX links.

• Prepared Test Plan and developed the test cases.

• Identified functional coverage points and did coverage coding

• Wrote system verilog assertions.

• Updated the functional checkers according to the requirement changes.

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