vlsi,verilog hdl

A BHISHEK CHAUHAN

E mail: *****************@*****.***

Ph No: 880-***-****

Address:*****, ***,********* ******** *********,UP-201016

CARRIER OBJECTIVE:

To become a part of an innovative organization that utilizes my knowledge and

capabilities to the maximum extent and to grow up with experience and constant

i mprovement in “Semiconductor/VLSI Front-end” domain for the functional area of

D igital/ASIC/SOC/VIP’s design and verification.

ACADEMIC QUALIFICATION:

B.TEC H (Electronics & Communication Engineering) from A BES Engineering

College G haziabad, UP Technical University, Lucknow, w ith an aggregate

of 64.01%(till 7th semester).

H I G H ER SECONDARY EXA M I NAT ION f rom RRSVMIC Dhampur,UP Board

A llahabad with an aggregate of 79%.

S ECONDARY SCHOOL CERT I F ICATE f rom RRSVMIC Dhampur,UP Board

A llahabad with an aggregate of 67.6%.

T ECHNICAL SKILLS:

H DL Language :Verilog HDL

Tools Used : Modelsim, Xilinx

M icroControllers :8051,PIC16

Operating Systems :Windows, Linux

P rogramming Languages :C, Python, Assembly

A lso Familiar with : RTL Designing, Simulation,

Synthesis, Verification concepts.

CERTIFICATES & INDUSTRIAL TRAINING:

Six weeks industrial t raining on V LS I Technology, ASIC front-end flow

using MO DE LS I M tool from I N FOSE M I TEC HNOLOG IES, NO IDA.

Six weeks certificate course in E mbedded Systems f rom C MC, Delhi.

Successfully completed a six week internship under I I T Bombay on p ython

t extbook companion project.

K EY PROJECTS HANDLED:

M AJOR PROJECTS:

Designing a m icrocontroller on FPGA using Verilog H D L .

FPGA Implementation of baseband modulation for transceiver of 802.16e

( W I MAX) u nder the supervision of C ADENCE DES IGN SYSTE M, NO IDA

experts.

M I N I PROJECTS:

Designing an A MBA APB T I M E R using Verilog H D L.

Designing a D ual Port R A M using Verilog H D L.

Designing an A LU using Verilog H D L .

Designing a F I FO using Verilog H D L.

Designing a F S M using Verilog H D L.

Touch detector.

AREA OF INTERSTS:

D igital Electronics

V LSI Front End Designing

M icroprocessor(8085)

ACHIEVEMENTS:

Solved a textbook “ Fundamentals Of Thermodynamics” by “B. Claus And R.

E . Sonntag” using P YT HO N p rogramming language.

Solved a textbook “ Engineering Physics” by R .A.Yadav & S.K.Srivastava ”

using P Y T HO N p rogramming language.

W inner of district level science quiz competition in class,9 th,10th,11th .

EXTRA CURRICULUM ACTIVITIES:

Participated in the technical quiz competition at ABES Engineering College

Ghaziabad in march 2013.

P resented a technical research paper on “ Designing a microcont roller using

Verilog H D L ” in the “ National Conference on Broadband & Optical F iber

T echnologies” conducted by A BES Engineering College, Ghaziabad on March

13-14,2015.

Working with a NGO “Light De Li teracy”.

PERSONAL DETAILS:

Date Of Birth: 1st january, 1994

Father's name: Mr Sudhir Kumar

L anguages known: Hindi,English

Nationality : Indian

M arital Status: Single

Hobbies: Listening to music,reading news

papers, watching news debates

D ECLAIRATION:

I solemnly declare that above details were t rue best of my knowledge and belief.

Date:

Place:

(ABHISHEK CHAUHAN)

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