CURRICULUM VITAE

Manogna Gummadi

Email: manogna.john@@gmail.com

Mobile:+91-879*******

Bangalore

Entry level positions as Design/Verification Engineer preferably in ASIC

domain.

OVERVIEW

Good understanding in Digital logic design& Electronics fundamentals

Good understanding of the ASIC design flow

Experience in Verilog HDL to write synthesizable RTL, self-checking test

benches&

Test benches in System Verilog

Very good knowledge on Verification methodologies(UVM)

Experience in using industry standard EDA tools for the Front-end Design and

Verification

Knowledgeable in STA concepts and timing calculations .

PROFESSIONAL QUALIFICATIONS

One year experience as a teaching assistant in Bapatla Women's Engineering

college

Duration: July 2013-April 2014

Maven Silicon Certified Advanced VLSI Design and Verification course

From Maven Silicon VLSI Design and Training Center, Bangalore

Duration : July 2014-December 2014

Duration of internship January 2015 -present

ACEDEMIC QUALIFICATIONS

Bachelor of Technology in Electronics and Communication

Nagarjuna University, Andra pradesh

Aggregate : 81%

Intermediate

Secondary Board of intermediate,Andra pradesh

Percentage : 84 %

Secondary Education

Board of Secondary Education,Andra pradesh

Percentage : 81 %

TOOLS & TECHNICAL SKILLS

HDLs : Verilog

HVL : System Verilog

Verification

Methodologies : Coverage Driven Verification

TB Methodology : UVM

EDA Tools : Modelsim and Xilinx-ISE

Domain : ASIC Design Flow, Digital Design methodologies

Knowledge : RTL Coding, FSM based design, Simulation,

Code Coverage,

Functional Coverage, Synthesis, Static Timing Analysis

Tool/Softwares : MATLAB,Pspice

Operating systems : Windows & Ubuntu

VLSI PROJECTS

AHB to APB Bridge Protocol Design

HDL : Verilog

TB Methodology : UVM (Universal Verification Methodology)

EDA Tools : Questa-Verification Platform and Xilinx-ISE

Description : AHB to APB Bridge interfaces an AHB to the

APB. Address, data and control signals from the AHB are latched to

simplify interfacing to the APB. An internal address map decodes the

address and generates signals for peripheral selection, eliminating

the need for an external decoder.

Architected the design and described the functionality using Verilog

HDL.

Designed the RTL model using Verilog.

Generated Code coverage for the RTL verification sign-off Synthesized

the design

Assertion based Verification of the RTL module using UVM.

AXI UVC - AMBA AXI4 Protocol Verification

HVL : System Verilog

Methodology : UVM (Universal Verification Methodology)

EDA Tools : Questa - Verification Platform

Description : The AMBA AXI protocol is targeted at

high-performance, high-frequency system and includes a number of

features that make it suitable for a high-speed submicron

interconnects. AXI UVC is a configurable UVM based verification IP.

It verifies the AXI protocol and generates the required functional

coverage

Architected the class based verification environment in UVM

Verified the protocol with single master single slave environment

Generated functional coverage for verification .

General purpose input/output Protocol Verification

HVL : System Verilog

Methodology : UVM (Universal Verification Methodology)

EDA Tools : Questa - Verification Platform

Description : GPIO IP the Controller Core is an interface between

APB compatible Master Device and GPIO interface Slave device .It has

1 to 32 I/O signals.By using GPIO we can implement the functions

that are not implemented with dedicated controllers in asystem. The

GPIO Core RTL is technology independent and fully synthesizable.

Architected the class based verification environment using UVM.

Verified the the Functionality using UVM.

Generated Functional coverage verification.

UART(Universal Asynchronous Receiver/Transmitter) IP core protocol

Design

HDL : Verilog

TB Methodology : UVM (Universal Verification Methodology)

EDA Tools :Questa-Verification Platform and Xilinx-ISE

Description :The UART core provides serial communication

capabilities, which allow communication with modem or other external

devices, like another computer using a serial cable Rs232 protocol.

This core is designed to be maximally compatible with industry

Standard National Semiconductiors' 16550A device.

Architected the design and described the functionality using Verilog

HDL.

Designed the RTL model using Verilog.

Generated Code coverage for the RTL verification sign-off Synthesized

the design

Assertion based Verification of the RTL module using UVM.

Router 1x3 - RTL design and verification

HDL : Verilog

HVL : SystemVerilog

TB Methodology : UVM

EDA Tools : Modelsim, Questa-Verification Platform and Xilinx-ISE

Description : ROUTER is a device that forwards data packets

between computer networks.

It is an OSI layer. It devices an incoming packet to an output based on

the address field contained the packet header.in this project it has one

master and three slaves. ROUTER RTL is fully synthsizeble.

> Architected the design and described and verified the functionality

using Verilog HDL.

> Generated Code coverage for the RTL verification sign-off Synthesized

the design

> Architecting the class based verification environment using UVM

> Verification of the RTL module using UVM

> Generation of functional coverage for the RTL verification

ACEDEMIC PROJECT

project details

Title : Designing of FIR BSF using modified

Hamming Window

Tool : Matlab

Role : project leader

Team strength : 5

Description : The system provides the narower main lobe width

and sharp transition band compare to Hamming window by using this technique

we can eliminate the noise and unwanted signals. Based on this system we

can implement the multi-tone signaling.

DECLARATION

I hereby declare that the information furnished above is true to the best

of my knowledge.

Place: Bangalore Signature: manogna.g

Reference on Request.

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