Design Project

MANOHAR B R

MTech in VLSI Design, Email ID : *******.******@***.**.**

VIT University, Chennai Campus Contact No. : +917*********

Chennai - 600127

Tamil Nadu, India

OBJECTIVE

• To pursue a challenging career in VLSI sector to utilize my technical skills and project experiences

while enhancing my knowledge and grow up with the organization through balanced learning and

application

EDUCATIONAL QUALIFICATION

Year of

Examination School/College Board/University Result/Aggregate

Passing

MTech VIT University, 8.08 CGPA (up to

VIT University Pursuing

(VLSI Design) Chennai 1st semester)

B.E G.M. Institute of Visvesvaraya

(Electronics & Technology, Technological 2013 73.58%

Communication) Davangere University, Belgaum

Anubhavamantapa Department of Pre-

12th (PUC) PU College, University Education, 2009 82.67%

Davangere Karnataka

Karnataka Secondary

K.J.N.V.S High

10th (SSLC) Education Examination 2007 91.36%

School, Davangere.

Board

TECHNICAL SKILLS

• Hardware Description Language: Verilog HDL

• Programming languages: C

• Cadence EDA Tools:

NC Sim

RTL Compiler

Encounter Digital Implementation

Virtuoso ADE

Spectre Circuit Simulator

Layout XL

• Assura DRC, LVS and QRC

• Scripting languages: PERL

• Xilinx ISE, ModelSim

• Familiar with advance Low Power Methodologies

• Technology Libraries: gpdk180, gpdk45, PTM32 (MOSFET), PTM32 (FINFET)

AREAS OF INTEREST:

• ASIC Design

• Memories

• Physical Design

• Custom Layout

• Verification and validation

PROJECTS – POST GRADUATE LEVEL:

1. Project Title: Low power adiabatic circuit designing using FinFET

Supervisor: Dr. V S Kanchana Bhaaskaran, DEAN, SENSE department.

Duration: 6 months

Publication: Science china international Journal (ongoing)

Environment: Cadence EDA tools (Virtuoso ADE, Layout XL)

Brief Description: Full-Custom design of digital circuits using prominent ENERGY RECOVERY

CIRCUITS (2N2NP, 2N2P, PFAL, DCPAL, ICPAL and IPAL) was made. Considering 4/8 phases of

single and dual power clock operation, simulation and analysis was done for the wide frequency

range of 0.1MHz to 1GHz considering every input sequence. Comparison is done with popular logic

methodologies to optimize and enhance performance. Performance analysis is made on all modes and

PVT corner models of FinFETs and MOSFETs.

2. Project Title: Design, simulation and performance analysis of digital circuits.

Supervisor: Dr. V S Kanchana Bhaaskaran, DEAN, SENSE department.

Duration: 6 months

Environment: Cadence EDA tools (Virtuoso ADE, Layout XL, NC Sim and Encounter)

Brief Description: The Design of Schematic and Layout for Adder and Multiplier circuit was done

using static, dynamic and domino logics (SP3-DL, DCVSL, SDSL, SPLIT-PHASE VSL, CPL, CSL,

DPL, ECDL, DRDL and DCPAL). The circuits were designed in a semi-custom manner using

GPDK180 and Lower technology nodes ( Berkley PTM-32nm MOSFET, PTM32 FinFET library)

and Power, Energy and delay comparison has been done under various aspects like frequency, sub-

threshold mode, latency up to 2048 cascaded stages and fan-out. Leakage current in every phase of

clock was measured as it plays major role in Adiabatic Logic families.

PROJECTS – UNDER GRADUATE LEVEL:

1. Project Title: Semantic apprehending based landmark auto navigation of Robot using OCR.

Supervisor: Prof. Savita S Patil

Duration: 6 months (Team of 4 members)

Environment: JAVA, MYSQL, Eclipse

Brief Description: A robot was designed to navigate automatically using signboards. The Bot will be

stopped by pre-placed RFID and takes snap of signboard and Image will be sent via GPRS

automatically. Using OCR the image is interpreted and synthesized. The significant audio

announcement will be made about signboard, next action to be taken and hence vehicle will be

navigated thereafter.

PERSONAL SKILLS

• Willingness to learn new technologies

• Willingness to work hard in as a team

• Self-motivated

ACHIEVEMENTS:

• Bagged 1st prize in “A Hunt for India’s Super RoboGenius” workshop and competition held by

Robosapiens Technologies, at B.I.E.T Engineering College, Davangere.

• Selected as zonal winner in RoboOpus-2012 and was invited to participate in National level

competition in the month of May-2013 at IIT-DELHI.

• Awarded ‘Certificate of merit’ for becoming topper of the Institute during Xth Grade.

• Co-ordinated to organize a National Level Quiz Competition & State Level Technical

Symposium under WIZONICS Forum of Electronics & Communication Dept., G.M.I.T. in 2nd year.

• Led Kho-Kho team as a Captain in District level sports and ended as Runner-up, conducted by

Department of Youth Services and Sports, Karnataka.

• Completed Elementary Drawing Grade Examination (HIGHER) conducted by Karnataka

Secondary Education Examination Board.

• Got 6 Belts (up to Brown Belt-3rd Dawn) in the art of Shito-Ryu-Karate-Do.

• Attended workshops on JAVA, Mentor Graphics and TCAD.

PERSONAL PROFILE

• Name : Manohar B R

• Mother’s name : Nagarathnamma M G

• Father’s name : Rajappa B

• Date of Birth : 12 May 1991

• Marital status : Single

• Gender : Male

• Mother Tongue : Kannada

• Languages Known : Kannada, English, Hindi, Telugu

I hereby declare that the above information is correct and complete to the best of my knowledge and

belief.

Place: Chennai MANOHAR B R

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