verilog, VHDL, MATLAB, C/C++, PYTHON

YUE CHEN

***** ********* **, *** ****, Dallas, TX 75252

*********@********.*** 469-***-****

OBJECTIVE: Seeking a full time position in the field of ASIC/SOC/IP/FPGA Design utilizing knowledge in RTL

Design, Synthesis, STA, ARM, BIST and ICC tool.

EDUCATION

• THE UNIVERSITY OF TEXAS AT DALLAS, Richardson, Texas Expected May 2015

MSEE

• CHANGCHUN UNIVERSITY OF SCIENCE AND TECHNOLOGY, China June 2013

BS Physics

ACADEMIC EXPERIENCE

Laser Application Technology Laboratory, CUST, Changchun, China Aug 2012 – Apr 2013

Research Assistant

• Tested and evaluated the model machine made by professor with YAG laser-marking machine, and assisted the

professor to solve problems with the software of EZCAD. Installed the laser maker controller board machine, and

then controlled the machine through changing the parameters.

ACADEMIC PROJECTS

A Mini Stereo Digital Audio Processor (MSDAP)

• Developed an architecture for a MSDAP chip and implemented the designed system using VHDL.

• Verified system correctness by writing a testbench. Performed functional simulations using ModelSim.

• Synthesized RTL code in Design Vision. Verified the functionality of the netlist in ModelSim.

• Generated a chip layout from ICC and verified the chip size, power dissipation, clock tree and post-layout timing

closure.

UTD Pipelined Microprocessor

• Designed a 16-bit customized pipelined Microprocessor based on Harvard architecture using Verilog.

• Implemented the design on Nexys 4 DDR Artix-7 FPGA board.

• The board was interfaced with keyboard that was used to enter instructions.

• Displayed the output on a seven segment display on the board.

N-Body Problem Simulation using ARM Cortex-M4

• Developed c code to simulate the physical movement based on ARM Cortex-M4.

• Configured UART to achieve data transmission. Optimized the code, reduced the running time of the program.

• Created a GUI using Matlab for receiving data from UART, visualizing the simulation and outputting final

simulated position on text files.

Realization of UART System (IBM 130nm)

• Developed an architecture for UART system and verified the functionality of UART system using ModelSim.

• Designed schematics and layouts of standard cells, such NAND, AOI22, MUX2:1 and characterized the library.

• Accomplished synthesis and simulation for netlist, auto place and route for layout. Verified the design by DRC,

LVS, Static Timing Analysis.

SKILLS

• Programming Languages: Proficient in Verilog and VHDL, Familiar with Matlab, C/C++, python and Assembly

language (RISC).

• Tool Used: Cadence, Synopsys, Primetime, ICC, Xilinx ISE, Siliconsmart, ModelSim, Quartus II, Hspice.

• Operating Systems: Ubuntu Linux, UNIX, Windows (all versions).

RELEVANT COURSE

VLSI Design Application Specific Integrated Circuit Design

Advanced VLSI Design Microprocessor System

Advanced Digital Logic Digital Signals Processing I

Computer Architecture Design and Analysis of Reconfigurable System

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