Noble Alex

**** **, **** ******, ** *** •Gainesville, Florida • 32608

CELL 267-***-**** • E-MAIL acpxx6@r.postjobfree.com

Objective To obtain an internship/full-time position (Summer/Fall 2015) as a Hardware Engineer which will help me use,

develop and enhance my relevant work and academic experience.

Education Master of Science in Electrical and Computer Engineering (Jan 2014 – Aug 2015(anticipated))

University of Florida, Gainesville (FL) (GPA: 3.3/4.00)

Bachelors in Electronics Engineering (Aug 2008 – June 2012)

K.J Somaiya College of Engineering, Mumbai (India) (GPA: 3.33/4.00)

Relevant Computer Architecture, Embedded Systems, Real Time Operating Systems

Coursework VLSI Circuits and Technology, Fault Tolerant Computer Architecture, Reconfigurable Computing

VLSI Device Design, Parallel Computer Architecture, Advanced VLSI Design, Computer Networking

Skills Programming : C, C++, VHDL, Verilog, System Verilog, MatLab, Perl

Methodology/Tools : UVM, ModelSim, VCS, Xilinx ISE, V-tunes, Cadence Virtuoso/Spectre, H Spice

Operating System : Windows, Linux

Work Experience Arrow Devices, Bangalore (India) (June 2013 – Dec 2013)

Design Verification Intern

Developed verification solution for MIPI UniPro v1.41 and v1.61 specific to l1p5 and l2 layer. Modified the BFM

specific to l1p5 and l2 layer along with test cases and debugging of issues.

Mathematics Instructor for Senior High School Students (Aug 2012 – May 2013)

Taught entry level & advanced level engineering mathematics to senior high school students.

Air India, Mumbai (India) (Aug 2012 – Dec 2012)

Engineering Intern

Worked with aircraft engineers on installation and removal of all electrical components, instrument components

and radio equipment. And also software debugging of the In -Flight Entertainment Sys.

Projects Simulator for a Compressible Multiphase turbulence application (Parallel Computer Architecture-Spring15)

Developed a simulator for the above exascale system application using task dependency and data flow a nalysis.

Power Optimized All Digital Phase Locked Loop (Advanced VLSI-Spring15): Front-end to back-end design and

verification of an all digital phase locked loop. Wrote the RTL and test bench using VHDL, schematic level

validation and layout was done using Cadence Spectre and Virtuoso.

From Planar to Multi-gate transistors: the case for FinFets (VLSI Device Design-Spring15)

Wrote a research paper focusing on the reasons for the switch from planar to non -planar structures in FET’s.

1-D Time-Domain Convolution (Reconfigurable Computing-Fall14): Built the SRAM interface (both read and

write) needed for the project. VHDL was used to implement the same and built on an FPGA.

4x1 SRAM Memory Design (VLSI Circuits and Technology-Fall14): Designed and tested a 4x1 SRAM memory

which included the basic 6T memory cell, sense amplifier and a pre-charge circuit.

Fault-Tolerant Wireless Data Acquisition Sys for BMI Applications (Fault Tolerant Comp Arch-Fall14): Worked

on researching (finding out advantages and disadvantages) and implementing different types of information

redundancy techniques needed for the project. The implementation was done using MATLAB and VHDL

Parametric Cache Simulator (Computer Architecture-Spring14): Designed a cache simulator which had a

memory hierarchy of L1 data cache, victim cache and main memory using C.

Real-Time Priority based Pre-Threaded Web Server (Real Time OS-Spring14): Developed a web server that

interacts with web clients, where the server consisted of main threads(higher pri ority) and worker threads.

Home Automation and Security on RX-63N and Sakura (Embedded Systems-Spring14): Built a security system

which could detect motion, sense temperature and smoke on the Sakura board using C and notify the base

station i.e the RX-63N.

Automated Baggage Handling System (Senior year project): Built the controller for sending information to the

host computer and decoding information from RFID Reader module. C was used to program the controller.

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