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Engineering Engineer

Location:
India
Posted:
May 28, 2015

Contact this candidate

Resume:

RESUME

ARUNKUMAR.C

Cell - +918*********

Email - *********.*@*****.***

CAREER OBJECTIVE

To obtain a rewarding position in the field of engineering that will allow me to utilize my engineering

skills and to co-ordinate with a team of highly experience professionals for my personal as well as

corporate growth.

EDUCATION DETAILS

Year of

Qualification Institute University / Board Percentage Passing

Bachelor of Bahubali College of Visvesvaraya

2014 67.00

Engineering (E&C) Engineering, Technological

Shravanabelagola University (VTU)

Government Polytechnic Department of

Diploma (E&C)

Nagamangala, 67.40

Technical Education 2011

Mandya

Government Karnataka

10th (SSLC)

65.60

Pre-university College Secondary School 2008

Basaralu, Mandya Education

Examination Board

PROJECT DETAILS

Topic: Implementation of 8 bit multiplier in Verilog using Reversible Logic gates.

Simulator used: Cadence NC Launch and RTL Compiler.

Abstract: In this project we have designed 8-bit multiplier using Reversible gates; compared

with normal 8-bit multiplier it reduces the Delay, Depth of the circuit, and usage of gates.

Reversible logic gates are very much in demand for the future computing technologies as they

are known to produce zero power dissipation under ideal conditions.

Duration: 3 Months

SKILLS

Soft Skills: Leadership quality, Team player, Self-motivated.

Core Skills: Microcontroller, Microprocessor, VLSI, Analog/Digital circuit design & analysis,

Semiconductors.

WORK EXPERIENCE:

Company: Schneider Electric IT Business India private ltd.

Experience: 6 Months.

Designation: QA Engineer.

Responsibilities: IQC, Inspection of Electronic components, PCB’s, IGBT’s, Capacitors, wires &

Cables, SCR, Motion & Drive products.

EXTRA CURRICULAR ACTIVITES:

Hobbies: Playing cricket and Kabaddi.

Strength: Never give up, Quick learner, Positive thinker.

Achievements: Paper on part of our work entitled “Implementation of 8-bit Multiplier in Verilog

Using Reversible Logic Gates” has been communicated to IFRSA International Journal of

Electronics Circuits and systems-IIJECS.

Paper presentation: Papers were presented in college technical feiesta-13&14.

Others: Volunteered in FIESTA-13, a National level technical fest held at Bahubali College of

engineering, Shravanabelagola.

PERSONAL DETAILS:

Permanent address: Arunkumar.c s/o Chandru

#30, Chikkayagati (V)

Honakere (Hobli)

Nagamangala (Tq)

Mandya-571432

Date of birth: 08/05/1993

I hereby informed that all the above mentioned information is correct according to my knowledge.

Place: Bengaluru Arunkumar.c



Contact this candidate