Design Electrical Engineer

DIVIN HONNAPPA [pic]

Objective: Dedicated electrical engineer actively seeking full-time entry

level position in the field of design or verification.

Academic Qualification

Master of Science: Electrical engineering at University of Texas at Dallas,

Richardson, Texas Dec 2014

Bachelor of Engineering: Electronics and comm. engg at Visvesvaraya

Technological University, India July 2012

Relevant Coursework at UTD:

Advanced VLSI Design Analog Integrated Circuit Design RF and Microwave

Systems Engineering VLSI Design

Advanced Digital Logic Testing and Testable Design Semiconductor Processing

Technology

Technical Skills and software:

Tools: EDA Cadence Virtuoso, Hspice, EDI Encounter in Cadence, CPP Sim

Viewer, GEDA, ngspice, UVM.

Scripting tools: C++,Perl, VHDL, VERILOG, System Verilog.

Simulation Tools: CADENCE, TETRAMAX, Synopsys (Waveview, Design Vision,

Nano Time), Mentor Graphics Modelsim, Assura, MATLAB.

Platforms: UNIX, Windows.

Areas of Interest : ASIC Design, Verification, Memory Design, FPGA

prototyping, Circuit Simulations and testing, Digital Logic

implementation, Analog Circuit Design, High Speed Serial Link, RTL design &

synthesis using Verilog/VHDL, Static Timing Analysis

Professional Experience:

Design Engineer, Scalable Systems Research Labs. Inc

Dec 2014- Present

. Currently working in Design Verification team, designing DDR3 interface

by editing and simulating system verilog codes using Modelsim of Mentor

Graphics.

. Part of the Analog/Mixed Signal design team working on CML(Current Mode

Logic) based HSSL(High Speed Serial Link) for Hybrid Memory Cube(HMC) in

28nm Technology.

. Responsible for transistor level schematic design, verification and

implementation of CML based SerDes(Serializer/Deserializer) block and

CDR(Clock and Data Recovery) block of the HSSL for HMC.

RF Engineering intern, GTL USA

Aug 2013-Dec 2013

Ericsson Market and T-Mobile Market: Ericsson market UMTS Testing and NSN

Market 4G LTE Performance Testing

. Performed RF performance testing of AT&T carriers UMTS network sites and

of T-Mobile carriers 4G LTE network sites.

. Extracted and analyzed data log files using TEMS investigation 14.5 and

QXDM for field implementation

. Performed download and upload measurements, CSFB and mobility test

verifying the LTE intra-site handovers and sector swaps.

Academic Projects:

1k-bit SRAM Design (using Cadence IBM 130nm technology)

. Designed a 1K bit SRAM addressing memory cell read stability and writ-

ability issues through proper transistor sizes.

. Constraint was Area vs. Delay optimization through custom layout.

. Results show a worst case read time of 220ps, write time of 182ps and

area of 17.46 sq. um/bit.

23b X 23b Multiplier Design in schematic form (using Cadence IBM 130nm

technology)

. Designed a 23 x 23 Multiplier using Booth-2 multiplication algorithm.

. Constraint-Area vs. Delay optimization.

. Results show a worst case delay of 2.72ns and area of 338 sq. u

Low power High-Speed Fast Settling Op-Amp design (using Cadence IBM 0.35um

technology schematic form)

. Designed a low power high-speed Operational amplifier addressing

saturation of transistor issues through proper transistor sizing.

. Constraint- Gain vs. Slew rate optimization is done.

. Results show a gain of 80 dB and a slew rate of 10 V/ s.

16-bit ALU and STANDARD Cell Library Generation (IBM 130nm technology)

. A Verilog code is written to perform 16-bit ALU operations and all the

required general logic gates are designed.

. The code is synthesized in Synopsys Design compiler to obtain the mapped

net list.

. Cadence SoC Encounter is used for automatic placement and routing of the

design.

. Performed static timing analysis using Synopsys nanotime and created a

new cell library is generated using Liberty NCX.

Digital circuits design and analysis.

. Designed and tested Asynchronous D-Flipflop along with implementing

various circuits on FPGA board.

. Performed scripting of various sequential circuits in verilog, Perl and

C++ and implemented and verified those circuits.

Fault detection and testing.

. Implemented various sequential and combinational circuits and performed

multi-level optimization on them.

. Performed ATPG, Fault simulation, Boundary Scan and BIST analysis on CUT

using Synopsys tool's Design Vision and Tetramax.

Activities: . Member IEEE at UTD, Vice-Chairman UTD Comet Debate Society.

WORK-Authorization: F-1 VISA with EAD

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