Electrical Engineering Design

DHARIT SURA **** Canyon Crest Dr, Apt H***,

817-***-****, ********@***.*** Riverside, CA 92507

OBJECTIVE: Seeking an Internship position in Hardware Design and Architecture.

EDUCATION

M.S, Electrical Engineering, University of California, Riverside GPA: - 3.6/4.00 June 2016

B.Tech, Electrical Engineering, Narsee Monjee Institute of Management Studies (NMIMS) University,

Mumbai, India GPA: - 3.2/4.00 June 2014

TECHNICAL SKILLS

EDA Tools: Cadence Virtuoso, Cadence Encounter v7.1, Syncad Verilogger, Tina PRO, Kiel Microwind

Programming: C, C++, Assembly (8086, 80386, 8051), Matlab, CUDA

Operating Systems: Windows, Linux (Ubuntu & RedHat)

Hardware Languages: Verilog, VHDL

RELEVANT COURSEWORK

Advanced Computer Architecture Quantum Computing

GPU Architecture and Parallel Programming Applied Quantum Mechanics

Solid-State Devices Stochastic Process

Radio-Frequency Integrated Circuit Design Math Methods for Electrical Engineering

ELECTRICAL ENGINEERING PROJECT

Jan 2014 – March 2014

Performance Modeling of the CPU

Modeled the various CPU parameters

Compared the naïve method with the Software optimized version of matrix multiplication

Further the influence of multi-threading on program performance was analyzed by using GCC

compiler and Mersenne Prime Validation Software

Jan 2014 – March 2014

Training Recurrent Neural Networks, VSC Lab, UC Riverside

• Analyzed which areas of the Neural Network had the most execution time

• Designed an algorithm for CUDA implementation in Nvidia Tesla K20

• Achieved a 10-12% boost up in the training process

• Also figured out that a partial implementation gave us overheads of data transfer between Device

to Host and vice-versa

September 2014 – Dec 2014

Battery Management System, VSC Lab, UC Riverside

• Interfaced the BMS of Texas Instruments with the Xilinx ATLYS FPGA board

• Researched and improved the present State-of-charge and State-of-health readings from batteries

• Designing fast and efficient ways for charging

8-bit CPU, Senior Design Project, NMIMS University Aug 2013 - March 2014

• Created a complete flow for Integrated Circuit (IC) design, right from RTL to the physical

layout design

• Successfully Implemented the design using a 5-Stage RISC pipeline

DHARIT SURA 3201 Canyon Crest Dr, Apt H294,

817-***-****, ********@***.*** Riverside, CA 92507

• Designed the ALU from the transistor level

• Performed Synthesis, placement and routing on Qflow

16KB 6T SRAM-cell, Senior Design Project, NMIMS University Feb 2013 - May 2013

• Planned and created a 6T SRAM Cell in layout and schematic on Microwind tool

• Designed NMOS and PMOS by changing the W/L ratio and interfaced it with 4:16 Row decoder

and sense amplifier

Intelligent Traffic Control Systems, Junior Design Project NMIMS University Feb 2012 - May 2012

• Designed an intelligent adaptive traffic control system with three members

• Surveyed and maximized throughput for lanes having the most traffic, and also communicated

with near-by signals to reduce area-wide traffic congestion.

RELEVANT ACADEMIC WORK

Robotics Certified Workshop, Rajiv Gandhi Institute of Technology, Mumbai (Feb 2012)

Online course: Quantum Computing UC, Berkeley (Feb 2013)

Nano VLSI and Intermediate VLSI Program, Atkom InfoTech (Oct 2012-May 2013)

Embedded Systems Certified Program, Thinklabs Mumbai, India (June 2012)

Online Course: Introduction to Parallel Programming, Udacity (Jan 2014)

WORK ELIGIBILITY & AVAILABILITY

US Permanent Resident

Available: Summer and Fall 2015

Contact this candidate