Project Engineer

VLSI Trained Engineer

T. Satya rao,

Room No-**6,

Ashwatha Hostel,

IIITD&M,

Email:********.********@*****.***

Chennai-600127

Mobile: +919*********

Carrier Objective:

To build a constructive career in a leading organization which has

an excellent inspiring environment to realize my intellectual abilities,

acquired knowledge and comprehensive exposure while contributing

vigorously for the progress of the company.

Education:

. Pursuing M.Des in Electronic Systems in IIITD&M Kancheepuram in

Chennai.

. B.Tech, Electronics & Communications Engineering, from JNTU KAKINADA

with 68.61%.

. 10+2 (Intermediate) from Gayatri Jr college, Vizianagaram, with

88.50%.

. 10th (SSC) Bapu vidya nikethan High School, Vizianagaram, with 90.50%

Training:

. Trained in VLSI ASIC Verification engineering at NV LOGIC, Hyderabad

from December 2010 to February 2012.

Technical Skills:

. Design And Verification of RAM,FIFO, PISO by using Verilog

. Verilog Programming

. Cadence, Multisim, Matlab

. Good knowledge in control systems

. Good at C language

Tools Used:

. Linux OS,

. ModelSim, Xilinx

. Programming Languages: Verilog (HDL's),

M.Des PROJECT:

Title : FIR Filter architecture for SDR

My Role : Developed the RTL code for Multiplier, Adder and test

bench

Language : Verilog

Description : Developing an optimum design to decrease the complexity

of a Digital FIR Filter. The proposed architecture is expected to consume

less power by decreasing the computational time using Sub expression

elimination technique.

PROJECTS UNDER TAKEN:

Project 1:

Title : RAM design and Verification

Team size : 8

My Role : Developed the RTL code for RAM and Test bench

Language : Verilog

In this project 256X16 bit RAM is designed and verified with test

bench environment. 256 bytes Ram consists of 8 address lines, read, write

enabling pins. The coming data is stored in the respective flops by using

the address lines and the write enabling pin. If we want to take the data

from the flops we can access the data by using the same addressing lines

and the read pin. In this design Multiplexers and flip flops are used.

Project 2:

Title : Parallel input and Serial output

Team size : 4

My role : Developed RTL code and Verification

Language : Verilog

Designed test bench environment for parallel input

serial output.

B. Tech Project:

Title : Monitoring Patient body temp & heart beat using Zigbee

Communication.

Team Size : 4

My Role : Developed C code & Hardware for Zigbee communication.

Language : Embedded C

This Project consists of one Transmitter and Receiver to monitor the

patient health condition by sensing body temp and heart beat. Patient's

body Temperature and heart beat is calculated using respective sensors and

these sensors are interfaced to Micro Controller. The main communication

between transmitter and receiver is implemented through Zigbee. Both Tx

module and Rx module has 2x16 LCD displays to know the communication

details. Total module is implemented using AT89C51 Micro Controller.

Strengths:

. Quick learning with Result Orientation

. Believes in Team Play

. Flexible and committed

. Good communication

ACHIEVEMENTS:

. Cultural committee coordinator- "BLITZ09" (Symposium).

. School Topper in 10th standard.

Personal Profile:

Name : T. Satya rao

Father Name : T. Demudu

Date of Birth : 20-06-1989

Sex : Male

Languages Known : Telugu & English

Hobbies

: Reading books, browsing

Marital Status : Single

Declaration:

I am confident on my ability to work in a team. I hereby declare that

the above information furnished is true to the best of my knowledge.

Place: Chennai,

Signature

Date: 5/3/14

T. satya rao

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