Project Design
Resume:
NAVEEN SILVERI Email id : ******.*********@****.***
Mobile: +91-886*******
CAREER OBJECTIVE:
To become a Physical Designer in an esteemed organization that provides challenging
environment, where I could extract my skills and work for the up-liftmen of the
Organization.
Professional Work experience
• Currently Working as a Physical Design Trainee Engineer at Orange Semiconductors
Pvt Ltd from Nov, 2014 to till date
Worked as a Project Trainee in Shastra Micro Systems from June 2013 to Nov 2014
•
TECHNICAL PROFICIENCY:
• Experience in 180nm, 90nm, 45nm technologies.
• Experience in Full Chips and blocks in 180nm and 45nm.
• Experience in CAD flow development for PnR flow.
• Experience in Physical Verification and Assisted to debug rule file for standard layout
process and checks perform DRC, LVS ERRORs, ERC.
• Operating Systems: Linux, Unix, Windows.
Backend Tools: SOC Encounter, primetime, IC Compiler Synopsys
•
HDL Language: Verilog
•
Scripting Language : TCL,PERL
•
M.Tech in VLSI and EMBEDDED SYSTEMS from Lords Institute of Engg. &
•
M.Tech in VLSI & EMBEDDED System from Lords Institute of Engg & Tech, JNT
•
University Hyderabad November 2013.
B.Tech in ECE from Anwarul –Uloom Engg. & Tech, JNT University Hyderabad.
•
Diploma in ECE from Q.Q.Govt Polytechnic, SBTET, Hyderabad.
•
NAVEEN SILVERI Email id : ******.*********@****.***
Mobile: +91-886*******
Physical Design Project 1:
Project Name: DTMF DESIGN IMPLEMENTATION.
No. of macros: 15
Technology: 65nm
Frequency: 200 Mhz
Instance count: 5k
Clocks: 2
Role and Responsibilities:
• Floor Planning, power Planning, Timing Closure and Congestion aware placement.
Static Timing Analysis with SI and OCV aware, Fixing Antenna Violations.
•
Physical Design Project 2:
Project Name: Block Level PNR and Area and Optimization
No. of macros: 29
Technology: 40nm
Frequency: 125 Mhz
Instance count: 550k
Role and Responsibilities:
Responsible for timing closure
•
Avoid Congestion issue by proper blockages and region approach
•
Implemented buffer insertion algorithm using PERL to find a common point
•
in data path
Implemented timing ECO using TCL script.
•
Physical Design Project 3:
Project Name: Block Level PNR and Static Timing Analysis
No. of macros: 45
Technology: 40nm
Frequency: 125 Mhz
Instance count: 149k
Role and Responsibilities:
NAVEEN SILVERI Email id : ******.*********@****.***
Mobile: +91-886*******
Responsible for timing closure
•
Avoid Congestion issue by proper blockages and region approach
•
Implemented buffer insertion algorithm using PERL to find a common point
•
in data path
Implemented Timing ECO using TCL script.
•
STRENGTHS:
• Good communication skills, Quick learner, Team player.
Attitude: - Positive, Friendly.
•
Declaration:
I hereby declare that statements made are true and complete to the best of my knowledge.
Place: Bangalore
Date: 22/05/2015 (Naveen silveri)
Contact this candidate