Design Engineer

Upasana Aggarwal mailto:*******.********.***@*****.***

PH: +63-915*-***-***

OBJECTIVE

To pursue a challenging career and to be a part of progressive organization that gives

scope to enhance my knowledge, skills and to work hard to achieve individual, group and

organizational objectives.

INDUSTRIAL EXPERIENCE

Design Automation Engineer (2011 2015)

● First line support and single point of contact for all the environment related

issues for Bangalore HIP design team consisting of more than 250 engineers.

● Responsible for development and support of design and compute environment for

HIP BU for multiple process nodes

● Working with cross site counterparts to develop solutions to improve efficiency,

address roadblocks for the design teams.

● Co owner for DB dashboard, a web based solution which is used across multiple

sites to reduce turnaround time for multiple environment issues. This particular

solution was submitted for Intel DTTC. This solution is widely used by the DA

community across geos.

● Worked on setting up the environment and infrastructure for the first TSMC project at

HIP.

● Owner of the web based tool to help designers sign off for milestones online.

● Co developer of the Vampire tool, this is an interface for creating ADE XL

testbenches and running simulations.

● Contributed to DART, a web based internal SOC delivery tool for central runs. Few

modules were owned by me.

● SVN/GIT repository for code infrastructure.

● Developed out of box solution for fast synchronicity operations across multiple

sites for Design management tool resulting in 10x improvement.

● Hardware key contact, coordinating all design and engineering computing issues.

● Managing & providing technical guidance/support to the new joiners, enabling them

with the required group accesses.

Design Automation Intern (2011)

● Worked on a tool which aimed at enhancing emulation potential for pre silicon bug

detection and post silicon bug reproduction.

● This tool provides a solution where most of the errors are identified in the

pre silicon stage itself and hence reduce the time and cost of validation at a later

stage.

STRENGTHS

● Good problem solving ability and analytic skill to solve the problem efficiently.

● Good team player and have excellent interaction skill to coordinate and work within a

team.

● Good Technical Skill with an aptitude for programming.

● Deliver output in less time without losing efficiency.

EDUCATIONAL QUALIFICATION

● B.Tech (Computer Science & Engineering) from VIT University, Vellore, 2011,

Secured 8.97 CGPA

● Class XII (ISC) from The Asian School, Dehra Dun, 2006, Secured 90.2%

● Class X (ICSE) from The Asian School, Dehra Dun, 2004, Secured 92.2 %

SKILLS

Programming Languages erl, PHP, JavaScript, Jquery, C, C++

: P

Operating Systems

: UNIX/LINUX, Windows

Databases

: MySQL, Oracle

Data Structures, Algorithms, Internet Programming, Operating

Other Courses

: Systems, DBMS

Design Sync, VLW, MAS, Cadence tools, CodeIgniter, SVN, GIT,

Utilities:

MS Office

PERSONAL DETAILS

Age : 26 years, 27 8 1988

Gender : Female

Marital Status : Married

Languages : English, Hindi, Punjabi

I hereby declare that the information furnished above is true to the best of my knowledge.

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