Design Technical

Email: **********@*****.***

JINESH K B Phone: +91-974*******

DOB: April 27, 1991

Career Objective

To seek a challenging career in VLSI design, where I can apply and enhance my knowledge

and technical skills.

Area of interest: ASIC/SoC Physical design, Static Timing Analysis

Academic Credentials

2013 to May 2015 M-Tech : Microelectronics and VLSI 7.88/10

National Institute of Technology Calicut

2008 to 2012 B-Tech : Electronics and Communication 66.93%

Vidya Academy of Science and Technology, Thrissur

University of Calicut

2006 to 2008 Plus Two 84.50%

Technical Higher Secondary School, Chettuva

2005 to 2006 AISSE 68.60%

S.V.N.C.S,Kodakara

Technical skills

Programming Languages VHDL, Verilog HDL,C and PERL

EDA Tools Cadence RTL Compiler, SoC Encounter, Xilinx-ISE, NCSim

Hardware Virtex-2pro, Sparten-3E FPGA boards

Academic Projects

M-Tech

1. ASIC implementation of, real time stereo vision algorithm using DCT

Modification to the existing Sum of Absolute Difference algorithm has been proposed to

minimize the power and delay, by utilizing the energy compaction property of discrete cosine

transform and to design an ASIC for the same using 180 nm technology.

2. Object detection using IR sensor and FPGA

B-Tech

1. ANT Robot

In this project, ability of a group of robots that communicate by ZigBee is used to implement

an efficient weight carrying mechanism.

2. RF based speed limiter

Declaration

I hereby declare that the details furnished by me above are true to the best of my knowledge

Jinesh K.B

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