Project Design
Resume:
Gundu S M Eswara Kumar,
Madhavaram,
Tadepalligudem, E-Mail: acppm3@r.postjobfree.com
West Godavari District (A.P),
Pin code -534145. Mobile No: +919*********
Career Objective:
Seeking an entry level position in a company to utilize my technical and analytical skills.
Explore myself fully and realize my potential every time to work as a key member in challenging
and creative environment.
Educational Background:
Discipline/ Board/ Year of
Examination Percentage
School/college
Specialization University Passing %
VIT University,
VIT 7.67(CGPA)
M.tech VLSI Design 2015
(up to 3rd sem)
University
vellore
Electrical and Sri Vasavi
JNTU
B.Tech Electronics Engineering 2012 79.76
University
Engineering College,
(Kakinada)
pedatadepalli
Science + Maths Aditya Junior
Intermediate Stream College, State 2008 92.4%
Tadepalligudem
Z.P.High school,
S. S. C S.S.C State 2006 77.16%
Madhavaram
Skill Set :
• EDA Tools: CADENCE-Virtuoso,NC Sim,RTL Compiler,SOC encounter,ModelSim,
• Programming skills: C,C++
• Hardware Description Language: Verilog HDL.
• Scripting Languages: Perl and TCL.
Project work:
• Design of Ring Amplifier for Switched Capacitor Circuits
Duration: 4 months
Description: This project is aimed to design a ring amplifier for switched capacitor applications. This ring
amplifier provides low power and gives stable performance at lower technology nodes (90nm).in general
op-amps are key elements in switched capacitor circuits but they consume more steady state power and
the performance degrades as going towards lower technology nodes. so, ring amplifier is a better
alternative to op-amps for switched capacitor applications.
• Low Power Clock Generation for Software Defined Radio
Duration: 4 months
Description: This project is aimed for the clock generation, pre dividers and post
dividers were designed using CADENCE VIRTUOSO tool and suitable values for
programmable divider were calculated for 4 different standards and modeled using
MATLAB with 2 PLL’s.
• Design Of Floating Point Multiplier Using Carry Save Adder
Duration: 4 months
Description: This project is aimed to reduce the area and power by reducing the partial products in the
multiplication portion such that we should code the program here I used verilog HDL for programming
and Model sim software for simulation and testing.
• Design Of Smart Car Parking System
Duration: 4 months
Description: This project is aimed to design car parking system which should be
automated like whenever there is empty slot then only gate will be open and it will show
the indication lamp where the slot is empty such that driver can place vehicle safely.
• Implementation of low power Radix-2 Butterfly Algorithm in ASIC
Duration: 2 months
Description: Implemented low power Radix-2 butterfly algorithm and did back-end
design in Cadence Encounter.
• Verification of Synchronous FIFO Controller
Duration: 4 months
Description: In this project I have designed FIFO controller. And then I have verified it
using Checker based verification topology. I have written modules for BFM, Checker,
Monitor using Verilog HDL and then integrating them all I have written top-module
testbench. I have written many test cases to test functionality of the design under test
(DUT), I have successfully done the verification for the Design.
Organization Skills:
Organizational and Analytical skills.
•
Self-motivated.
•
Always willing to learn.
•
Achievements:
Organized the project exhibition Event of TECH EUPHORIA 2010, A National Level
•
Technical symposium at Sri Vasavi Engineering College.
Participated in “Circutrics” conducted at C R Reddy College of Engineering.
•
Personal Profile:
Name : G.S.M.ESWARA KUMAR
13th Feb 1991
Date of Birth :
Father’s Name : G.KAMESWARA RAO
Permanent address : Madhavaram,
Tadepalligudem,
West Godavari District (A.P), Pin code: 534145.
Email : acppm3@r.postjobfree.com
Marital Status : Single.
Hobbies : playing Caroms, Cricket and Listening to Music.
Languages Known : English, Telugu.
Passport : K9443734
Date:
(G.S.M.Eswara Kumar)
Place:
Contact this candidate