Project Design

Syed Azhar

Email:*********.****@*****.*** Mobile: +91-

949-***-**** D/no 2-1-

**,********,

Metro city,HYD-

500018.

Objective

Getting into a progressive company, apply my skills which will

help for the development of organization and to

prove myself as a successful employee.

Professional Experience

3+ years of Experience in field of VLSI.

. Nov 1,2013 to till date working as " Sr.VLSI Designer" with

Trylogic Soft Solutions AP Pvt Ltd,Hyd.

. Jun 1, 2013 to Oct 30, 2013 worked as a freelancer.

. Jan 9, 2012 to May 31, 2013 worked as "VlSI Designer" with Logic

Systems,Hyd.

. May 3, 2011 to Sep 2011 as a "Trainee" in Sandeepani School Of

VLSI Design and Verification.

Trylogic Soft Solutions AP Private Limited is a software

development, web design & development services company that specializes in

creating tailor made custom applications for enterprises.

Professional Summary:

. Expertise and Exp in Advance Digital Design concepts

. Knowledge on verification using VMM

. Good knowledge of Verification using System Verilog

. Expertise in Verilog HDL RTL Coding

. Good Knowledge in VHDL

. Good Knowledge in Test bench development Using HDL

. Knowledge in Verification Using System Veriolg HVL

. Experience in Xilinx FPGA Design flow & its Architecture

. Hands on Experience in Synthesis, Place and Route tools for FPGA

. Practical experience of EDA tools Xilinx ISE, Altera Quartus II,

QuestaSim.

. Having practical experience with FPGA Boards (Xilinx).

. Programming and Debugging capabilities with FPGA boards

. Knowledge in SOC Protocols AMBA,AXI,ETHERNET,SPI,I2C,UART

. Excellent debugging skills

. Knowledge in CMOS circuit design

. Perl Scripting beginner.

. Adept in end-to-end development of projects from requirement analysis

to system study, designing, simulation, synthesis, documentation and

implementation.

Roles and Responsibilities:

. As a RTL Designer, involved in understanding the requirement study,

design and development.

. I have been involved in the development of several applications of

various kinds - security applications, low power,high speed and low

area applications.

. Performed simulation on projects using Verilog standards using Xilinx

and Modelsim Tools.

. Designing and developing academic projects (IEEE and Non-IEEE)

. Designing of programming on FPGA Interfaces using LCD, Seven Segment

and VGA.

. Implemented Different Actions for Application Flow.

. Developed Helper classes for interacting Verilog and system Verilog..

. My role in these engagements has covered requirement gathering,

architecting, application and Design, guiding team members, coding,

maintenance and documentation.

Technical skills

> Technology : VLSI

> Languages : Verilog HDL, System Verilog, C,

C++ Concepts

> Electronic Design Packages : Xilinx ISE, Model SIM, ChipScope

pro,Matlab,

Microwind,QCADesigner.

Project 5: Data Encoding Techniques for Reducing Energy Consumption for NOC

Networks.

Language of Implementation: Verilog/VHDL

Third Party Tool: Xilinx ISE (for synthesis and simulation) & Modelsim.

Operating System: Windows 7

Description: In this project we have designed three type transitions for

Couple Switching by comparing with the self-switching. As the technology

improves in NOC the networks on the links increases,as the links increases

the flow of information will become more complex to make a good efficiency

in the output we have designed type1 type2 and type 3 transitions which

performs the operation as Encoder and Decoder. In encoder we have used

different kinds of the blocks which performs the majority in the operations

of designing of data encoding techniques.

Project 4: Design of a Pong Game

Language of Implementation: Verilog/VHDL

Third Party Tool: Xilinx ISE (for synthesis and simulation),Digilent Adept

(For FPGA Prototyping).

Operating System: Windows 7

Description: In this project we have designed a pong game controller which

can be played using an FPGA Board .We have designed a different kind of

modules for display of game on monitor with suitable resolution.On the FPGA

Board(Digilent Basys 2) we have interfaced with switches which made as

controllers to move the ladders up and down so that the ball hits the

ladders.

Project 3: Advance Encryption Standard For Cryptographic Applications

Language of Implementation: Verilog/VHDL

Third Party Tool: Xilinx ISE (for synthesis and simulation) & Modelsim.

Operating System:Windows 7

Description: It's an encryption project, this project is designed using the

rounds and each of every round there is particular operation going on such

as add round key,shift rows,mixed columns and sub bytes and in this

project we have used s-box as ROM which will store the values already as

format of the table. This project is mostly used in cryptographic

applications for sending security info of data while transferring the

information between two communicating blocks.

Project 2: Creating a Class Based Verification Environment using System

Verilog

Language of Implementation: System Verilog

Third Party Tool: Model Sim & Questa sim(For Verification)

Operating System: Windows 7

Description: In this project we have chosen RAM as a DUT for which Read and

Write Operation has been done using AMBA-APB protocol and developed a class

based environment. The environment consists of following modules-

transaction, generator,bfm(Bus Functional Model),monitor and scoreboard.

Transaction consists of inputs required for performing various operations

of the DUT.

Project 1: Finger Print Based Vehicle Access Security System

Language of Implementation: Assembly

Third Party Tool: Keil (for programming modules).

Operating System:Windows 7

Description: It's a security based project for Vehicle, when we access

fingerprint (owner) through finger print module then only we can start the

bike otherwise it is restricted to start a bike.

Extra-curricular Activities:

. Training the employees about various technologies

. Conducting workshops on different technologies.

. Collecting the IEEE papers and designing the project codes

. Handling the project codes and documentations

. Giving support to trainers and programmers

Education

B-Tech -JNTUH university,first class with distinction(73.8),2011.

Intermediate -SRK college,first class with distinction(79.4),2007.

SSC -Shanthinikethan,first class with distinction(79.5),2005.

Passport Details

Passport Number :L2232803

Date Of Issue :12/06/2013

Date Of Expiry :11/06/2023

Personal Details

Name : Syed Azhar

Father's Name : Syed Mahamood

Date of birth : 1st JUNE 1990

Languages Known : English, Urdu, hindi and

Telugu

Nationality : Indian

(SYED AZHAR)

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