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Project Engineering

Location:
San Mateo, CA
Salary:
2.5
Posted:
May 13, 2015

Contact this candidate

Resume:

PALISETTI PALLAVI

Contact No: +91-994*******

E-mail:***********@*****.***

CAREER OBJECTIVE

. To be associated with an organization that provides me an opportunity

to intensify my skills with the latest cutting edge technology and to

be a part of a team that consistently operates towards excellence.

EDUCATIONAL CREDENTIALS

Discipline/

Examination Specialization Name of the Board/ Year of %

Institution University Passing

JNTU-H 2013 80.52

B-tech Electronics & SLC's

Communication Institute

Engineering of engineering

and

technology,

Hyderabad.

MPC Sri Chaitanya

Intermediate (Mathematics, junior State 2009 86.3

Physics, college,

Chemistry) Hyderabad.

Siddhartha

SSC SSC High School, State 2007 82

Hyderabad

EXPERIENCE:

. Company Name: BHARAT ELECTRONICS LIMITED (BEL) in Bangalore.

. Designation : Graduate Apprentice Trainee

. Department : C-D&E (Radar Signal Processing).

. Projects Handled in BEL

1. Digital Waveform and Timing generation module for Radar Application

Digital Waveform & Timing generator (DWF&TG) is hardware based

on Xilinx Kintex 7 series FPGA.The module has three main functions.

First it generates the Radar waveform or CW signal at 60 MHz, which

is up converted to C-band in the Up converter module. Second it

generates all the timing & control signals required by all the

Synthesizer modules. SMC Signal is generated based on the dwell

message from RC. Third, it can also be programmed to work in BITE

mode and generate BITE waveforms and BITE controls.

. Brief Job description : PCB Fabrication, assembly and testing

o Design of schematic for PCB using orcad in Cadence and FPGA

board testing.

o Overall project components selection according to data sheets

and project requirements.

o Coding & debugging the project PCB using Xilinx tool flow.

o Writing test procedures for executing board with VHDL code bit

files.

2. Antenna Beam Control Unit for Athulya

ATULYA is a ground based fully active phased array radar which

operates in X-band. Beams are steered both in Azimuth and Elevation by

digital phase shifters integrated in each of T/R module and full 360o

coverage in Azimuth direction is achieved by rotation of the Antenna Unit

in horizontal plane. Antenna Beam Control Unit (ABCU) is the top level

Controller in the BSU hierarchy, which provides interface with the Beam

Scheduler of Radar Controller (RC) via Exciter-Receiver Unit (ERU)and

Plank Controllers through high speed serial link. This is a FPGA based

controller for computation and distribution of beam data to 64 plank units

and collecting status from various other subsystems like Planks, Power

Supply Junction Box etc.

. Brief Job description : Design of schematic for PCB using orcad in

Cadence, board layout design, Assembly and testing.

o Generation of Orcad schematics

o Procurement of components and making Purchase requests and

follow-up

o Mother-board layout and interfaces design

o PCB fabrication, assembly and testing

o Engineering documentation

KNOWLEDGE IN SOFTWARE:

. Programming Skills : C, C++, Xilinx ISE Design 14.7, Pin Planning

Using Plan Ahead, VHDL and CADENCE 16.6.

. Operating Systems : Windows XP, Windows7.

KEY SKILLS

> Self-Confidence & Possess Positive Attitude

> Ability to work individually and in a group

> Sound communication skills along with good leadership and

interpersonal skills

> Self-motivated, sincere, hard working and Doing Things on Time.

PERSONAL PROFILE

Name : Palisetti pallavi

Father's Name : Palisetti Venkat Ramaiah

Date of Birth : 17-May-1992.

Address : H.No-2-41, Shantinagar, Vansthalipuram, Hyderabad,

Andhra Pradesh.

Nationality : Indian.

DECLARATION

I hereby declare that all the above mentioned particulars are true and

genuine to the best of my knowledge and belief.

Date: 12-05-2015

Place: Hyderabad.

(PALISETTI PALLAVI)



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