Project Engineer
Resume:
CURRICULUM VITAE
MANOJ KUMAR REDDY T D e-mail:
*******@**********.***
#**/*, *****************,*******(mandal)
Phone: +91-949*******
Anantapur(Dist),Andhra Pradesh-515571
Career Summary
To excel in a creative and challenging environment using innovative
technologies in the field of Digital Design and deliver the maximum towards
the growth of the Organization. I believe once I achieve this growth will
invariably follow.
Education
Qualification Name of Program / Course Studied Percentage Year of
Institution passing
M.Tech JNTU,Anathpur,A Digital Electronics and 2009-2011
.P Communication Systems 62 %
B.E SSIT,Bangalore Electronics & 58 % 1996-2001
University communications
INTERMEDIATE Vijayavani Maths physics Chemistry 79.1 % 1994-1996
Junior College,
Chowdepalli,
Chittor
District, AP.
SSC Sri Saraswathi English, Telugu, 70.7 % 1994
Vidya Mandir, Hindi,Maths,Science,Social
Kadiri, AP.
Project work Details
Organization name Designation/ Period Years of experience
cource
ANALOGIC CONTROLS INDIA Project Dec-2010 to July 8 Months
LTD, Hyderabad engineer 2011
/M.Tech
LRDE,DRDO Bangalore Trainee Nov 1999 to 3 Months
Engineer/ B.E Jan-2000
Experience Details:-
Organization name Designation Period Years of experience
JNTUA College of Lecturer July-2013-till 2 years
Engineering,Anantapuramu date
M.S. Engineering College Lecturer Jan-2012 to 1.4 years
June-2013
Ewas Technologies Pvt Associate Mar 2007 to 2.6 years
Ltd, (Auto TEC Engineer Oct-2009
group),Bangalore
Madanapalli Institute Of Teaching July 2004-July 2.0 years
Technology &Science, Assistant 2006
Madanapalli
S.V.Technologies, Hardware Jan 2002-Feb 2004 2.0 years
Hyderabad Engineer
Subjects taught in JNTUA : Digital Logic Design, Digital IC Applications,
Structural Digital System Design, Electronics devices and circuits theory
and lab.
Conferences and journals:-
. I presented a paper on "Hardware design of safety arming mechanism
using FPGA" for the
International conference on emerging trends in Engineering(ICETE)
conducted by NAMNIT,NITTE
.
. I presented Journal paper on "Implementation and Customization of
UART in
Xilinx FPGA" in International Journal of Combined Research &
Development (IJCRD)
eISSN: 2321-225X; pISSN: 2321-2241 Volume: 2; Issue: 1; January -
2014
. I presented Journal paper on "Hardware Design of Safety Arming
Mechanism using FPGA" in International Journal of Combined Research &
Development (IJCRD ) eISSN:2321-225X; pISSN:2321-2241 Volume: 2; Issue:
5; May -2014
Skills
. Good Communication Skills.
. Exhaustive experience in handling complex requirements and problems.
. Coordinating the entire team in handling the task effectively and
efficiently.
. Maintaining a good relationship and trust with the management and
clients alike.
Subjects studied in M.Tech:
Embedded system concepts, Digital system Design, wireless
communication, Digital Communication Techniques, Coding Theory and
Techniques, Detection &Estimation of signals, HI-speed Networks,
Microcomputer system design, Advanced Digital Signal processing,
Adaptive Signal processing, Image processing, Advanced Computer
Architecture
Technical Skills
. Languages : C,VHDL, Verilog
. Software tools : Xilinx, Altera
Max Plus II MultiSim Orcad
. Hardware Programming : EPROM,CPLD,EPLD,FPGA
programming.
. Testing Skills : HARDWARE &
SOFTWARE Testing
. Protocols and standards : ARINC 429,
UART, MIL_STD 1553B
> M.TECH Project carried out in ANALOGIC CONTROLS INDIA LIMITED.
> Project :Design of Electronic control unit(ECU) for Safety arming
Mechanism(SAM)using FPGA
. Technology : ANALOG AND DIGITAL DESIGN
. Organization : ANALOGIC CONTROLS INDIA LTD
. Designation : Project Engineer-R&D
. Roles & Responsibilities:
V FPGA Coding, Synthesys, Simulation
V FPGA( SPARTAN-3) Programming
V Hardware Testing, debugging
V Design of Digital circuits using XILINX ISE Tool
V Preparation of Project documents
Safety Arming Mechanism (SAM) is a modular sub-system of the unit to
ensure safety of the unit during handling, transport, storage, launch
phases of the unit and also in actuation of the unit It consists of an
Electronic Control Unit (ECU) and a motorized Arming Mechanism (AM).
ECU is provided with hardware and software safety interlocks which are
removed at different stages in a sequence and finally trigger the
firing circuits at desired time.
1. The design of ECU shall be a FPGA based sub-system with an Voltage:
28 4 V and an Current: < 500mA.
2. A dual output (for 28V & 5.5V/3.3V) using miniaturized wide range DC-
DC converter will be employed.
3. All the input commands shall be isolating using opto-couplers and
outputs will be interfaced to logic controller
through Schmitt trigger for noise reduction.
4. An UART is implemented in the FPGA for external communication.
5. A NVRAM is provided for logging of all the inputs and outputs of FPGA
for every 5msec.
6. The relation between outputs and inputs of the FPGA is implemented
through a Digital Logic.
7. All timings are derived through a 10MHz clock source.
8. A hydrostatic switch will be provided which shall be initially closed
for depth below 8 meters and get opened when it senses a depth of more
than 10 2 meters. Alignment of two interrupts and charging of firing
circuit capacitors shall take place only after conformation of both
OBC II command(28v Latched signal) and self generated signal at t= t0
+ 20 sec. Triggering of both firing circuits shall take place only on
receipt of signal from either of the impact switch. The system will be
completely sealed as it is having under water application.
> Projects carried out in LRDE, Bangalore in Digital Data
communications Field
> Project.:" Clock recovery and Synchronization Of Digital Data
Communication System "
Project Description: The project used to recover the clock from the
transmitted data and synchronization of the digital data The circuits in
the projects as follows
Clock Recovery :. The receiver requires proper clock information to decode
the received data without error . The clock recovery circuit is used to
recover the clock information form the received data stream.
Synchronization: It is required to recognize the start and end of each
frame to separate the various fields from frame. The Synchronization
circuit uses the sync bit format to achieve. A suitable algorithm should be
devised to achieve Synchronization even in the presence of imitation.
Field Combination : The frame consist of three parts they are,8 - bit
Synchronization slot, 8-bit control signal slot & 16-bit data slot .All
these are generated by different sections but before frame transmission all
these bits have to be grouped together to form a single frame .
> Projects carried out in EWAS Technologies in Avionics Field-Embedded
systems
> Project.: "BIT ERROR RATE SYSTEM (BER) Using Altera-Max-Plus -II
CPLD"
No of Units Done :04
Client: ISRO Bangalore
Description of the project: The project consisting of two sections
transmitter and receiver BER equipment
detects the data from the transmitter is read by receiver correctly or not
.If it read correctly. The error is zero
other wise it read the errors, some of the circuits description is as
follows.
Transmitter End: It consisting of the following circuits.
Data generator: It generates pseudo random data (2^15-1) and (2^23-1) code
lengths from i/p clock.
Encoder: It encodes the data in phase and quarter phase of desired
algorithm to the receiver end.
Receiver End: It consisting of the following circuits
Decoder: It decodes the data in phase and quarter phase of desire algorithm
from the Tx end.
Error Detector: It to the reader the errors in the data receiver for (2^15-
1) and (2^23-1) code length.
Presale circuit: It prescale the clock for display the clock on the
frequency counter and switching: It is used for display the errors and
exponent on LED display Keypad & LCD display : Selection are selected from
the keypad and displayed on LCD display using GPIB\IEE interface .Controls
are given from the keypad using GPIB circuits (local code ) controls also
given from the IEEE interface (remote ) from the computer .
> Projects carried out in EWAS Technologies & SIERRA Circuits Pvt.LTD
IN AVIONICS FIELD
* Team size : Four
* Technology : Embedded (Avionics)
* Organization : EWAS Technologies & SIERRA Circuits Pvt
LTD
* Designation : Associate Enginee
* Roles & Responsibilities:
V Inspection,BOM component checking
V Debugging
V CPLD, FPGA, EPROM,FLASH Programming
V Design of Digital circuits
V Board level and system level testing
V Participating in Technical review with Hardware design
Group
V Interest in the Design field and updating the new
technologies
V Preparation of Test documents, Production Test plan,
Acceptance Test plan and Reports
> Project.4:Radar Interface Card(RIF)& Radar Video Interface
Card(RVIF)
No of Units Done:100
Client: BEL, Ghaziabad
* Roles & Responsibilities:
V Design and testing of Digital circuits
V FPGA, flash Programming
V Preparing Acceptance Test Plan(ATP)
This VME based slave card capable of Interfacing to two External Primary
Radar Sources and two External Secondary IFF Sources. Primary Analog video
inputs (LIN/LOG/MTI) from the two radar sources shall be adjusted for
offset and gain using front panel potentiometers. Then one of the two
primary radar sources shall be selected. From the selected radar source the
final output shall be one among the three types of videos
(LIN//LOG/MTI).Secondary Analog Video inputs (IFF) from two radar sources
shall be adjusted for gain and offset using front panel potentiometers.
Then the selected secondary video shall be again subjected to software
programmable gain adjustment under the control of Host. Digital inputs from
the primary radar sources, namely ACP, SHM, SYNC and EOR shall be
conditioned by means of protection, pulse discrimination and validation.
There shall be a provision to select Single ended or Differential Inputs.
Control and software programmability can also be done using serial port
under on-board micro-controller host.
The Radar Video Interface Card(RVIF)card shall conduct POST by
comparing the looped back signals and the input signals. The card shall
also conduct on-line diagnostics by comparing the looped back signals and
input signals. Hence, the Card operates in three modes: POST, Normal and On-
Line Diagnostic
> Project.5:Aircraft Interface Box(AIB)
No of Units Done :20
Client: INS RAJALI, Arakhonam & INS HANSA, Goa.
* Roles & Responsibilities:
V Testing of AIB
V Carried ESS test in BEL,CPRI-Bangalore
V Board bring up, Debugging
V Installing the unit in Dornier Aircraft
V Interaction with INS-HANSA,INS-RAJALI clients
V
The Air Craft Interface Box is an air-borne unit designed to work as a part
of Avionics System. Aircraft Interface Box (AIB) is used to interface the
mike and the phone line outputs from the laptop to the HF communication set
of the aircraft. It is a passive device used for impedance matching only.
Aircraft Interface Box (AIB) is used to interface the Microphone and Serial
communication port of the laptop computer to the HF communication set of
the aircraft. It is a passive device used for impedance matching only.
Application S/W: Hurricane Version 0.54Testing: Adjust volume control to
maximum position in the laptop. Select Tx loop back in the software and do
the Tx short and long test by loop back method. The Environmental stress
screening (ESS) carried before the functional test. The ESS Tests are Pre
thermal Random vibration, Thermal cycling, Post thermal Random vibration,
Cath test, EMI/EMC tests.
> Project.6: Standalone Communication Unit(SACU)
No of Units Done :200
Client: BEL Bangalore
* Roles & Responsibilities:
V Testing of SACU
V Debugging
Standalone communication unit is analog circuit which amplifies the
signal. The circuit operates in single as well as Differential modes. In
Differential Tx mode by giving Differential signal from signal generators,
the Differential Tx pairs appears on both DRI as well as RADIO connectors
.In Differential Rx mode the Differential Rx pairs appears on both DRI as
well as SACU connectors. In single ended Record test the Differential
Signals on the TX pairs of the SACU Connector and the Differential Signals
on the RX pairs of the RADIO Connector gives the Single Ended TX Signal on
the BNC Connector. In Single end playback test the Differential RX pairs
appears on the SACU Connector.
> Projects.7:ATS-PCMCIA-1553:-Personal Computer Memory Card
International Association
No of Units Done :75
Client: BEL HAL,ISRO Bangalore
Roles & Responsibilities:
V Installing and Testing of PCMCIA-1553,PCMCIA-429 Card
V Debugging
V Interaction with Design Embedded Software Team
PC Card configuration memory and configuration process to be implemented
on xilinx Spartan II FPGA
MIL-STD-1553 bus isolation transformer is to be placed with in the cable
assembly The isolation transformer required to used are beta transformer
make DLVB-4113for direct coupled and dlvb-4213 for transformer coupled. It
consisting of two busses through which we can transmit,receive.It is
having 1553 controller FPGA,EPROM .FPGA is volatile so we require PROM
to store the code. FPGA will give command to the controller hardware
triggers.
> Project.8:ATS-PCI-MPAC:-Multiprotocal Avionic Card
No of Units Done :40
Client: BEL HAL,ISRO Bangalore
* Roles & Responsibilities:
V Installing and Testing of PCI-1553,PCI-429 CPCI-MPAC Cards
V Debugging
V Interaction with Design Embedded Software Team
MIL-STD-1553B Interface - Optional
The ATS-PCI-MPAC card's single function MIL-STD-1553B architecture emulates
a Bus Controller or 31 Remote Terminals or Monitor Terminal modes. Polling
and interrupt generation is also provided. The 1553B Channel comes with 64K
(DDC) static RAM.
Transformer and Direct Coupling
The cards are provided with the option of using them either in the
transformer mode or in the direct mode. A jumper is provided on the cards
to select the mode. The default connectivity is transformer-coupled mode.
ARINC-429 Interface - Optional
The card can be configured with up to 2 ARINC-429 controllers. Each
controller is configured with 2Tx & 4Rx channels and has 128 x 32 bit
static RAM.
Look-up tables loaded into the RAM enable the modules receive circuitry to
filter and sort incoming data by label and destination bit. It also
provides multilevel data specific interrupts or hardware triggers.
Other PCI cards done:PCI-1553,PCI-429,CPCI-1553,CPCI-MPAC
Personal Details
. Father's name : Mohan Reddy T.D
. Marital Status : Single
. Proficiency in language : English, Hindi, Kannada,
Telugu.
. Passport number : E9214029
. Pan card number : AVSPR3556P
. Permanent Address : 26-
4,Gandodivaripalli,Tanakal(mandal),Ananthpur(District),A.P.
. Phone : 084**-******
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