Name: DIVYA PADMAVATHI.C Phone:

+91-741*******

Email: acpldr@r.postjobfree.com

Reference: DINESH CHANDRASEKARAN, PERFECTVIPS

CAREER OBJECTIVE

Seeking a responsible position with an opportunity to widen my knowledge

and giving my best shot as a VLSI Professional to attain the objectives of

the company.

TECHNICAL SKILLS

Programming Languages:

Verilog

Systemverilog (except Coverage & Assertions)

C

C++

Verification Methodology:

UVM Basics

CERTIFICATIONS

Completed Certification course in Verilog and Systemverilog.

ACADEMIC PROFILE

B.E (Electrical & Electronics Eng), 2010-2014, Jayam college of eng & tech,

Anna University - 7.7 (CGPA)

HSC, 2010, Bharathidhasnar Matric Hr.sec.school - 81%

SSLC, 2007, Bharathidhasnar Matric Hr.sec.school - 87%

PROFESSIONAL AND INDUSTRIAL EXPOSURE

Participated in the Examination on "2008 INTERNATIONAL ASSESMENTS FOR

INDIAN SCHOOLS" in Science and Mathematics".

Participated in the symposium and presented the paper on "Robotic Surgery".

Participated in the workshop on "Enterpreneurship Orientation Programme".

Participated in the one day workshop on "CORPORATE 2 CAMPUS,an industry-

Institute Event".

AREA OF INTEREST

Digital Electronics

VLSI design & Verification

ACADAMIC PROJECT

Project "The System Verilog implementation of high speed

vedic mathematics multiplier using compressors

Project Description:

This project is aims to increase the speed of the multiplier.This involves

modern architecture to perform speed multiplication using ancient Vedic

maths techniques.It utilizes 4:2 compressors and novel 7:2

compressors.There is almost two times faster than the popular methods of

multiplication. With regards to area, 1% reduction is seen.

VERILOG PROJECT

Project ROUND-ROBIN ARBITER

Project Description:

This project involves Round-robin Arbiter Generation(RAG) tool. RAG tool

generates a design for a Bus Arbiter(BA).The BA is able to handle the

exact number of bus masters for both on-chip and off-chip.The RAG also

generates distributed and parallel hierarchical Switch Arbiter(SA). The

round robin token passes BA to reduce time spent on arbiter.The generated

arbiter is fair, fast and has a low and predictable worst case wait

time.The arbitration time is 256x256 for a terabit switch.The SA generated

by RAG meets the time constraint to achieve approximately six terabits of

throughput in a typical network

UVM PROJECT

Project APB Protocol

Project Description:

This project involves the development of complete UVC for APB

protocol. The work responsibility includes implementation of APB

Master, APB Slave, APB monitor/coverage, Scoreboard using UVM

methodology.

PERSONAL PROFILE

Father's Name : Mr. R.Chandrasekaran

Nationality : Indian

Date of birth : 23/11/1992

Gender : female

Marital status : Single

Phone : +91-741*******

Hobbies : Drawing,craft making.

Languages Known : English, Tamil and Kannada (localized).

DECLARATION

I hereby declare that the above particulars given by me are true and

correct to the best of my knowledge and belief.

YOURS TRULY,

C.DIVYA PADMAVATHI

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