Project Management

BHAGYASHRI SAYAJIRAO PATIL

B.E.(Electronics), M.E.(VLSI & Embedded System-Appearing)

Email: ***************@*****.***

Ph.: +919*********

OBJECTIVE

To be an enthusiastic member of progressive organization and to work hard with full dedication for

the achievement of organization objective, hence upgrading self skills and knowledge, adaptive to learn new

things to achieve excellence, innovation in the VLSI and embedded work domain.

ACADEMIC CREDENTIALS

Qualification / Degree Year of Passing College / Board/ University Grade / % Marks

M.E. VLSI & Embedded 2015 ADCET, Ashta, Sangali 65.71%

System Shivaji University (upto IIIsem)

B.E. Electronics 2011 T.K.I.E.T, Warananagar, Kolhapur 61.21 %

Shivaji University

HSC 2007 Kolhapur Borad 82.50 %

SSC 2005 Kolhapur Board 84.13 %

TECHNICAL SKILLS

Programming Languages : C, C++, VHDL

Design Tools : Xillinx ISE, Microwind, Mentor Graphics, MATLAB, MultiSim,

keil uvision IDE

INTERESTS

Designing Circuits

Travelling and visiting new places

ACADEMIC PROJECTS

M.E. Post Graduation Project:

Title : Implementation of On-chip delay measurement for small delay defect

Location : ADCET, Ashta, Sangali, Maharashtra

Software Packages : Xillinx 13.2

A Brief Description :

The objective of this paper presents a delay measurement technique using signature analysis, and a

scan design for the proposed delay measurement technique to detect small-delay defects. The proposed

method does not require the expected test vector because the test responses are analyzed by the signature

registers. Also an on-chip variable clock generator for double pulse width and latches for short measurement

time in scan design are generated. This measurement technique is coded in VHDL language and

implemented on FPGA Spartan 3E kit.

B.E. Graduation Project:

Title : GSM based Car Control System

Location : T.K.I.E.T, Warananagar, Kolhapur, Maharashtra

A Brief Description:

The project is to design and develop a system for monitoring the various parameters of vehicle,

sense accident, send status of vehicle on owners mobile. These processes could be controlled by NOKIA

3310 mobile handset which is fully based on GSM technology. The project is to control vehicle without any

efforts through mobile to send SMS to system.

ACCOLADES & EXTRACURRICULAR ACTIVITIES

Sr. College Name Workshop/ Competition Name Date/ Year Prize

No.

24th – 28th

1. ADCET, Ashta, One week ISTE Approved STTP on Participation

“Emerging Trends In VLSI &

Sangali November

Embedded Systems: A System On-Chip 2014

Approach”

21st Sept. 2013

BharatiVidyapeeth’s Workshop on “VLSI & EMBEDDED

2. Participation

SYSTEMS”

College of Engg,

Kolhapur

20th March

Project Competition of “EUREKA-

3. TKIET Warananagar, Participation

Kolhapur JIDNYASA 2K11 2011

th

Workshop on “RANG TARANG”

4. TKIET Warananagar, 19 Feb 2011 Participation

Kolhapur

2nd Oct 2010 2nd Prize

Group Event “INDRADHANU

5. TKIET Warananagar,

Kolhapur TRADITIONAL DAY 2K11

1st Aug 2010

Workshop on “INTELLETUAL

6. TKIET Warananagar, Participation

PROPERTY RIGHTS STUDIES”

Kolhapur

27th Sept 2008

Intellegent-Quist “BATTLE CITY 2K9’

7. TKIET Warananagar, Participation

Kolhapur

28th Jan 2009

8. J.J. Magdum College, National Level Poster Presentation Participation

“SPECTRUM 2K9”

Jaysingpur.

Member of “Council Committee” TKIET Warananagar 2009-2010.

Member of “EUREKA-JIDNYASA” TKIET Warananagar 2009-2010.

Member of “BATTLE CITY” TKIET Warananagar 2009-2010.

Technical Committee Co-head of “ESSA” TKIET Warananagar 2009-2010.

Executive Member of “HORIZON” TKIET Warananagar 2010-2011.

PAPER PUBLICATION

Presented a paper titled “Dynamic Memory Management For FPGA-Based Reconfigurable

Architectures” in International Conference on Recent Trends in Engineering Science and

Management on 15th March 2015.

Published a paper titled “Scan-Based Delay Measurement Technique by Signature Analysis to

Detect SDD: A Survey” in International Journal of Emerging Technology and Advanced

Engineering, Volume 5, Issue 3, March 2015.

Published a paper titled “Dynamic Memory Management For FPGA-Based Reconfigurable

Architectures” in International Journal of Electrical and Electronics Engineers, Volume 07, Issue 01,

Jan- June 2015.

Published a paper titled “Review on Digital Writing Instrument using Gesture Recognition” in

International Journal of Modern Trends in Engineering and Research, Volume 2, Issues 3; March

2015.

STRENGTHS

Ability to learn

Knowledge sharing

Persistent

Belief in what I do

WEAKNESSES

Perseverance

Over-thinker

PERSONAL DETAILS

1 Gender : Female

2 Marital status : Single

: 20th March 1990

3 Date of Birth

4 Languages Known : English, Hindi, Marathi.

5 Permanent address : Varad, A/P- Wategaon,

Tal- Walwa, Dist- Sangali

State- Maharashtra

Pin – 415410

DECLARATION

I hereby declare that the above mentioned details are correct to the best of my knowledge and I bear

the responsibility for the correctness of the above information.

Date:

Place: Miss. Bhagyashri Sayajirao Patil

Contact this candidate